diff --git a/Documentation/devicetree/bindings/gpu/adreno.txt b/Documentation/devicetree/bindings/gpu/adreno.txt index 37d769c9ea05..e87c9274bf32 100644 --- a/Documentation/devicetree/bindings/gpu/adreno.txt +++ b/Documentation/devicetree/bindings/gpu/adreno.txt @@ -124,9 +124,6 @@ Optional Properties: - qcom,pm-qos-wakeup-latency: Similar to the above. Driver votes against deep low power modes right before GPU wakes up from sleep. -- qcom,l2pc-cpu-mask-latency: - The CPU mask latency in microseconds to avoid L2PC - on masked CPUs. - qcom,gpu-cx-ipeak: CX Ipeak is a mitigation scheme which throttles cDSP frequency @@ -190,17 +187,6 @@ Optional Properties: Based on the ubwc mode, program the appropriate bit into certain protected registers and also pass to the user as a property. -- qcom,macrotiling-channels: - Specify the number of macrotiling channels for this chip. - This is programmed into certain registers and also pass to - the user as a property. -- qcom,l2pc-cpu-mask: - Disables L2PC on masked CPUs when any of Graphics - rendering thread is running on masked CPUs. - Bit 0 is for CPU-0, bit 1 is for CPU-1... - -- qcom,l2pc-update-queue: - Disables L2PC on masked CPUs at queue time when it's true. - qcom,snapshot-size: Specify the size of snapshot in bytes. This will override diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c index d99ecc1b0641..50131742bd07 100644 --- a/drivers/gpu/msm/adreno.c +++ b/drivers/gpu/msm/adreno.c @@ -1006,11 +1006,6 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev, &device->pwrctrl.pm_qos_active_latency)) device->pwrctrl.pm_qos_active_latency = 501; - /* get pm-qos-cpu-mask-latency, set it to default if not found */ - if (of_property_read_u32(node, "qcom,l2pc-cpu-mask-latency", - &device->pwrctrl.pm_qos_cpu_mask_latency)) - device->pwrctrl.pm_qos_cpu_mask_latency = 501; - /* get pm-qos-wakeup-latency, set it to default if not found */ if (of_property_read_u32(node, "qcom,pm-qos-wakeup-latency", &device->pwrctrl.pm_qos_wakeup_latency)) @@ -1760,10 +1755,6 @@ static int _adreno_start(struct adreno_device *adreno_dev) /* make sure ADRENO_DEVICE_STARTED is not set here */ WARN_ON(test_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv)); - /* disallow l2pc during wake up to improve GPU wake up time */ - kgsl_pwrctrl_update_l2pc(&adreno_dev->dev, - KGSL_L2PC_WAKEUP_TIMEOUT); - pm_qos_update_request(&device->pwrctrl.pm_qos_req_dma, pmqos_wakeup_vote); diff --git a/drivers/gpu/msm/adreno_dispatch.c b/drivers/gpu/msm/adreno_dispatch.c index dd4c8a897207..b971e206c0ae 100644 --- a/drivers/gpu/msm/adreno_dispatch.c +++ b/drivers/gpu/msm/adreno_dispatch.c @@ -1447,10 +1447,6 @@ int adreno_dispatcher_queue_cmds(struct kgsl_device_private *dev_priv, spin_unlock(&drawctxt->lock); - if (device->pwrctrl.l2pc_update_queue) - kgsl_pwrctrl_update_l2pc(&adreno_dev->dev, - KGSL_L2PC_QUEUE_TIMEOUT); - /* Add the context to the dispatcher pending list */ dispatcher_queue_context(adreno_dev, drawctxt); diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c index b1f1ba29a0c1..d2230c7a2930 100644 --- a/drivers/gpu/msm/kgsl.c +++ b/drivers/gpu/msm/kgsl.c @@ -4969,7 +4969,6 @@ int kgsl_device_platform_probe(struct kgsl_device *device) { int status = -EINVAL; struct resource *res; - int cpu; status = _register_device(device); if (status) @@ -5099,22 +5098,6 @@ int kgsl_device_platform_probe(struct kgsl_device *device) PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); - if (device->pwrctrl.l2pc_cpus_mask) { - struct pm_qos_request *qos = &device->pwrctrl.l2pc_cpus_qos; - - qos->type = PM_QOS_REQ_AFFINE_CORES; - - cpumask_empty(&qos->cpus_affine); - for_each_possible_cpu(cpu) { - if ((1 << cpu) & device->pwrctrl.l2pc_cpus_mask) - cpumask_set_cpu(cpu, &qos->cpus_affine); - } - - pm_qos_add_request(&device->pwrctrl.l2pc_cpus_qos, - PM_QOS_CPU_DMA_LATENCY, - PM_QOS_DEFAULT_VALUE); - } - device->events_wq = alloc_workqueue("kgsl-events", WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0); @@ -5151,8 +5134,6 @@ void kgsl_device_platform_remove(struct kgsl_device *device) kgsl_pwrctrl_uninit_sysfs(device); pm_qos_remove_request(&device->pwrctrl.pm_qos_req_dma); - if (device->pwrctrl.l2pc_cpus_mask) - pm_qos_remove_request(&device->pwrctrl.l2pc_cpus_qos); idr_destroy(&device->context_idr); diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c index cea6dbbcd5e8..05c7b7cc6b11 100644 --- a/drivers/gpu/msm/kgsl_pwrctrl.c +++ b/drivers/gpu/msm/kgsl_pwrctrl.c @@ -572,35 +572,6 @@ void kgsl_pwrctrl_set_constraint(struct kgsl_device *device, } EXPORT_SYMBOL(kgsl_pwrctrl_set_constraint); -/** - * kgsl_pwrctrl_update_l2pc() - Update existing qos request - * @device: Pointer to the kgsl_device struct - * @timeout_us: the effective duration of qos request in usecs. - * - * Updates an existing qos request to avoid L2PC on the - * CPUs (which are selected through dtsi) on which GPU - * thread is running. This would help for performance. - */ -void kgsl_pwrctrl_update_l2pc(struct kgsl_device *device, - unsigned long timeout_us) -{ - int cpu; - - if (device->pwrctrl.l2pc_cpus_mask == 0) - return; - - cpu = get_cpu(); - put_cpu(); - - if ((1 << cpu) & device->pwrctrl.l2pc_cpus_mask) { - pm_qos_update_request_timeout( - &device->pwrctrl.l2pc_cpus_qos, - device->pwrctrl.pm_qos_cpu_mask_latency, - timeout_us); - } -} -EXPORT_SYMBOL(kgsl_pwrctrl_update_l2pc); - static ssize_t kgsl_pwrctrl_thermal_pwrlevel_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) @@ -2229,13 +2200,6 @@ int kgsl_pwrctrl_init(struct kgsl_device *device) pwr->power_flags = 0; - kgsl_property_read_u32(device, "qcom,l2pc-cpu-mask", - &pwr->l2pc_cpus_mask); - - pwr->l2pc_update_queue = of_property_read_bool( - device->pdev->dev.of_node, - "qcom,l2pc-update-queue"); - pm_runtime_enable(&pdev->dev); ocmem_bus_node = of_find_node_by_name( @@ -2904,10 +2868,6 @@ _slumber(struct kgsl_device *device) kgsl_pwrctrl_set_state(device, KGSL_STATE_SLUMBER); pm_qos_update_request(&device->pwrctrl.pm_qos_req_dma, PM_QOS_DEFAULT_VALUE); - if (device->pwrctrl.l2pc_cpus_mask) - pm_qos_update_request( - &device->pwrctrl.l2pc_cpus_qos, - PM_QOS_DEFAULT_VALUE); break; case KGSL_STATE_SUSPEND: complete_all(&device->hwaccess_gate); diff --git a/drivers/gpu/msm/kgsl_pwrctrl.h b/drivers/gpu/msm/kgsl_pwrctrl.h index 4bb915a01055..e503a24b7621 100644 --- a/drivers/gpu/msm/kgsl_pwrctrl.h +++ b/drivers/gpu/msm/kgsl_pwrctrl.h @@ -57,19 +57,6 @@ #define KGSL_PWR_DEL_LIMIT 1 #define KGSL_PWR_SET_LIMIT 2 -/* - * The effective duration of qos request in usecs at queue time. - * After timeout, qos request is cancelled automatically. - * Kept 64ms default, inline with default GPU idle time. - */ -#define KGSL_L2PC_QUEUE_TIMEOUT (64 * 1000) - -/* - * The effective duration of qos request in usecs at wakeup time. - * After timeout, qos request is cancelled automatically. - */ -#define KGSL_L2PC_WAKEUP_TIMEOUT (10 * 1000) - enum kgsl_pwrctrl_timer_type { KGSL_PWR_IDLE_TIMER, }; @@ -149,9 +136,6 @@ struct kgsl_regulator { * @ahbpath_pcl - CPU to AHB path bus scale identifier * @irq_name - resource name for the IRQ * @clk_stats - structure of clock statistics - * @l2pc_cpus_mask - mask to avoid L2PC on masked CPUs - * @l2pc_update_queue - Boolean flag to avoid L2PC on masked CPUs at queue time - * @l2pc_cpus_qos - qos structure to avoid L2PC on CPUs * @pm_qos_req_dma - the power management quality of service structure * @pm_qos_active_latency - allowed CPU latency in microseconds when active * @pm_qos_cpu_mask_latency - allowed CPU mask latency in microseconds @@ -208,9 +192,6 @@ struct kgsl_pwrctrl { uint32_t ahbpath_pcl; const char *irq_name; struct kgsl_clk_stats clk_stats; - unsigned int l2pc_cpus_mask; - bool l2pc_update_queue; - struct pm_qos_request l2pc_cpus_qos; struct pm_qos_request pm_qos_req_dma; unsigned int pm_qos_active_latency; unsigned int pm_qos_cpu_mask_latency;