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staging: ccree: move request_mgr to generic bitfield ops
request_mgr was using custom bit field macros. move over to standard kernel bitfield ops. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -26,6 +26,11 @@
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#include "cc_bitops.h"
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#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP)
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#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \
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DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
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DX_AXIM_MON_COMP_VALUE_BIT_SHIFT)
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/* Register Offset macro */
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#define CC_REG_OFFSET(unit_name, reg_name) \
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(DX_BASE_ ## unit_name + DX_ ## reg_name ## _REG_OFFSET)
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@ -35,8 +35,6 @@
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#define SSI_MAX_POLL_ITER 10
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#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP)
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struct ssi_request_mgr_handle {
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/* Request manager resources */
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unsigned int hw_queue_size; /* HW capability */
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@ -502,6 +500,15 @@ static void proc_completions(struct ssi_drvdata *drvdata)
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}
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}
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static inline u32 cc_axi_comp_count(void __iomem *cc_base)
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{
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/* The CC_HAL_READ_REGISTER macro implictly requires and uses
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* a base MMIO register address variable named cc_base.
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*/
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return FIELD_GET(AXIM_MON_COMP_VALUE,
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CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET));
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}
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/* Deferred service handler, run as interrupt-fired tasklet */
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static void comp_handler(unsigned long devarg)
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{
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@ -521,25 +528,25 @@ static void comp_handler(unsigned long devarg)
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CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), SSI_COMP_IRQ_MASK);
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/* Avoid race with above clear: Test completion counter once more */
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request_mgr_handle->axi_completed += CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE,
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CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET));
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request_mgr_handle->axi_completed +=
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cc_axi_comp_count(cc_base);
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while (request_mgr_handle->axi_completed) {
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do {
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proc_completions(drvdata);
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/* At this point (after proc_completions()), request_mgr_handle->axi_completed is always 0.
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* The following assignment was changed to = (previously was +=) to conform KW restrictions.
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/* At this point (after proc_completions()),
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* request_mgr_handle->axi_completed is 0.
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*/
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request_mgr_handle->axi_completed = CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE,
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CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET));
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request_mgr_handle->axi_completed =
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cc_axi_comp_count(cc_base);
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} while (request_mgr_handle->axi_completed > 0);
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/* To avoid the interrupt from firing as we unmask it, we clear it now */
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CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), SSI_COMP_IRQ_MASK);
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/* Avoid race with above clear: Test completion counter once more */
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request_mgr_handle->axi_completed += CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE,
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CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET));
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request_mgr_handle->axi_completed +=
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cc_axi_comp_count(cc_base);
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}
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}
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