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https://github.com/rd-stuffs/msm-4.14.git
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drm/i915: vlv: setup RPS min/max frequencies once during init time
When enabling runtime PM on VLV, GT power save enabling becomes relatively frequent, so optimize it a bit. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -3701,6 +3701,45 @@ static void valleyview_cleanup_pctx(struct drm_device *dev)
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dev_priv->vlv_pctx = NULL;
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}
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static void valleyview_init_gt_powersave(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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valleyview_setup_pctx(dev);
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mutex_lock(&dev_priv->rps.hw_lock);
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dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
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dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
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DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
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dev_priv->rps.max_freq);
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dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
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DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
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dev_priv->rps.efficient_freq);
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dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
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DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
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dev_priv->rps.min_freq);
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/* Preserve min/max settings in case of re-init */
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if (dev_priv->rps.max_freq_softlimit == 0)
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dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
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if (dev_priv->rps.min_freq_softlimit == 0)
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dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
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mutex_unlock(&dev_priv->rps.hw_lock);
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}
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static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
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{
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valleyview_cleanup_pctx(dev);
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}
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static void valleyview_enable_rps(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -3767,29 +3806,6 @@ static void valleyview_enable_rps(struct drm_device *dev)
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vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
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dev_priv->rps.cur_freq);
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dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
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dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
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DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
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dev_priv->rps.max_freq);
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dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
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DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
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dev_priv->rps.efficient_freq);
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dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
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DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
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dev_priv->rps.min_freq);
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/* Preserve min/max settings in case of re-init */
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if (dev_priv->rps.max_freq_softlimit == 0)
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dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
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if (dev_priv->rps.min_freq_softlimit == 0)
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dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
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DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
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vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
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dev_priv->rps.efficient_freq);
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@ -4533,13 +4549,13 @@ void intel_init_gt_powersave(struct drm_device *dev)
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i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
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if (IS_VALLEYVIEW(dev))
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valleyview_setup_pctx(dev);
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valleyview_init_gt_powersave(dev);
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}
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void intel_cleanup_gt_powersave(struct drm_device *dev)
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{
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if (IS_VALLEYVIEW(dev))
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valleyview_cleanup_pctx(dev);
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valleyview_cleanup_gt_powersave(dev);
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}
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void intel_disable_gt_powersave(struct drm_device *dev)
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