malhuda/msm-4.14
1
0
Fork 0
mirror of https://github.com/rd-stuffs/msm-4.14.git synced 2025-02-20 11:45:48 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

ARM: dts: msm: add device tree for mdm9607

Browse Source 
This is snapshot of device tree files as of msm-3.18.c8
'commit 69da6b6721b  (Promotion of kernel.lnx.3.18.c8-190717)'.

Change-Id: Ib1b2043f6fb55137244707c83c106e5fab24f9ad
Signed-off-by: Suresh Kumar Allam <allamsuresh@codeaurora.org>
Signed-off-by: Haribabu Gattem <haribabu@codeaurora.org>
This commit is contained in:
Haribabu Gattem 2019-10-31 16:44:24 +05:30 committed by Suresh Kumar Allam
parent b48282c68f
commit 540d8cb5fd
48 changed files with 9899 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

476
Documentation/arm/msm/msm_smp2p.txt Normal file
View File

@ -0,0 +1,476 @@
Introduction
============
The Shared Memory Point to Point (SMP2P) protocol facilitates communication of
a single 32-bit value between two processors. Each value has a single writer
(the local side) and a single reader (the remote side). Values are uniquely
identified in the system by the directed edge (local processor ID to remote
processor ID) and a string identifier.
Version and feature negotiation has been included in the design to allow for
phased upgrades of all processors.
Software Architecture Description
=================================
The data and interrupt coupling between processors is shown in Fig. 1. Each
processor is responsible for creating the outgoing SMEM items and each item is
writable by the local processor and readable by the remote processor. By using
two separate SMEM items that are single-reader and single-writer, SMP2P does
not require any remote locking mechanisms.
The client API uses the Linux GPIO and interrupt framework to expose a virtual
GPIO and a virtual interrupt controller for each entry.
=================
| |
-----write------>|SMEM item A->B |-----read------
| | | |
| ================= |
| |
| v
GPIO API => ------------ ======= Interrupt line ======> ------------
Processor A Processor B
Interrupt <= ------------ <====== Interrupt line ======= ------------
API ^ |
| |
| |
| ================= |
| | | |
------read-------|SMEM item A<-B |<-----write----
| |
=================
Fig 1
Design
======
Each SMEM item contains a header that is used to identify and manage the edge
along with an array of actual entries. The overall structure is captured in
Fig 2 and the details of the header and entries are covered later in this
section. The memory format of all shared structures is little-endian.
-----------------------------------------------
| SMEM item A->B |
| |
| ----------------------------------------- |
| |31 24| 16| 8| 0| |
| |----------|---------|----------|---------| |
| | Identifier Constant(Magic Number) | |
| |----------|---------|----------|---------| |
| | Feature Flags |Version | |
| | |Number | |
| |----------|---------|----------|---------| |
| | Remote Proc ID |Local Proc ID | |
| |----------|---------|----------|---------| |
| | Entries Valid | Entries Total | |
| |-----------------------------------------| |
| |
| |
| ----------------------------------------- |
| | Entry 0 | |
| | ---------------------------------- | |
| | | Identifier String | | |
| | |---------------------------------| | |
| | | Data | | |
| | |---------------------------------| | |
| |---------------------------------------| |
| ----------------------------------------- |
| | Entry 1 | |
| | ---------------------------------- | |
| | | Identifier String | | |
| | |---------------------------------| | |
| | | Data | | |
| | |---------------------------------| | |
| |---------------------------------------| |
| - |
| - |
| - |
| ----------------------------------------- |
| | Entry N | |
| | ---------------------------------- | |
| | | Identifier String | | |
| | |---------------------------------| | |
| | | Data | | |
| | |---------------------------------| | |
| |---------------------------------------| |
-----------------------------------------------
Fig 2
The header of each SMEM item contains metadata that describes the processors
using the edge, the version information, and the entry count. The constant
identifier is used as a magic number to enable extraction of the items from a
memory dump. The size of each entry depends upon the version, but the number
of total entries (and hence the size of each SMEM item) is configurable with a
suggested value of 16.
The number of valid entries is used to indicate how many of the Entries Total
are currently used and are current valid.
---------------------------------------------------------------------------
|Field Size Description Valid Values |
---------------------------------------------------------------------------
| Identifier 4 Bytes Value used to identify |
| Constant structure in memory. Must be set to $SMP |
| Useful for debugging. (0x504D5324) |
---------------------------------------------------------------------------
| Local 2 Bytes Writing processor ID. Refer Processor ID Table 3|
| Processor |
| ID |
---------------------------------------------------------------------------
| Remote 2 Bytes Reading processor ID. Refer Processor ID Table 3|
| Processor |
| ID |
---------------------------------------------------------------------------
| Version 1 Bytes Refer to Version |
| Number Feature Negotiation Must be set to 1. |
| section. |
---------------------------------------------------------------------------
| Feature 3 Bytes Refer to Version |
| flags and Feature Negotiation |
| section for details. |
| bit 0 SSR_ACK Feature Supported when set to 1 |
| bits 1:31 Reserved Must be set to 0. |
---------------------------------------------------------------------------
| Entries 2 Bytes Total number of Must be 0 or greater. |
| Total entries. |
---------------------------------------------------------------------------
| Entries 2 Bytes Number of valid Must be between 0 |
| Valid entries. and Entries Total. |
---------------------------------------------------------------------------
| Flags 4 Bytes |
| bit 0 RESTART_DONE Toggle for every restart |
| bit 1 RESTART_ACK Toggle to ACK remote |
| RESTART_DONE |
| bits 2:31 Reserved Must be set to 0. |
---------------------------------------------------------------------------
Table 1 - SMEM Item Header
The content of each SMEM entries is described in Table 2 and consists of a
string identifier and a 32-bit data value. The string identifier must be
unique for each SMEM item. The data value is opaque to SMP2P giving the client
complete flexibility as to its usage.
----------------------- --------------------- -----------------------------
| Field | Size | Description | Valid Values |
------------|----------|---------------------|-----------------------------
| | | | |
| Identifier | 16 Bytes | Null Terminated | NON-NULL for |
| String | | ASCII string. | valid entries. |
| | | | |
------------|----------|---------------------|-----------------------------
| Data | 4 Bytes | Data | Any (client defined) |
------------ ---------- --------------------- -----------------------------
Table 2 - Entry Format
The processor IDs in the system are fixed and new processors IDs will be
added to the end of the list (Table 3).
-------------------------------------------------
| Processor Name | ID value |
-------------------------------------------------
| Application processor | 0 |
-------------------------------------------------
| Modem processor | 1 |
-------------------------------------------------
| Audio processor | 2 |
-------------------------------------------------
| Sensor processor | 3 |
-------------------------------------------------
| Wireless processor | 4 |
-------------------------------------------------
| Modem Fw | 5 |
-------------------------------------------------
| Power processor | 6 |
-------------------------------------------------
| TrustZone processor | 7 |
-------------------------------------------------
| NUM PROCESSORS | 8 |
-------------------------------------------------
Table 3 - Processor IDs
SMEM Item
---------
The responsibility of creating an SMEM item is with the local processor that is
initiating outbound traffic. After creating the item, the local and remote
processors negotiate the version and feature flags for the item to ensure
compatibility.
Table 4 lists the SMEM item base identifiers. To get the SMEM item ID for a
particular edge, the remote processor ID (Table 3) is added to the base item ID
for the local processor (Table 4). For example, the Apps ==> Modem (id 1) SMEM
Item ID will be 427 + 1 = 428.
---------------------------------------------------
| Description | SMEM ID value |
---------------------------------------------------
| Apps SMP2P SMEM Item base | 427 |
---------------------------------------------------
| Modem SMP2P SMEM Item base | 435 |
---------------------------------------------------
| Audio SMP2P SMEM Item base | 443 |
---------------------------------------------------
| Sensors SMP2P SMEM Item base | 481 |
---------------------------------------------------
| Wireless SMP2P SMEM Item base | 451 |
---------------------------------------------------
| Power SMP2P SMEM Item base | 459 |
---------------------------------------------------
| TrustZone SMP2P SMEM Item base | 489 |
---------------------------------------------------
Table 4 - SMEM Items Base IDs
Version and Feature Negotiation
-------------------------------
To enable upgrading without breaking the system and to enable graceful feature
fall-back support, SMP2P supports a version number and feature flags. The
combination of the version number and feature flags enable:
1) SMP2P software updates to be rolled out to each processor separately.
2) Individual features to be enabled or disabled per connection or edge.
The version number represents any change in SMP2P that breaks compatibility
between processors. Examples would be a change in the shared data structures
or changes to fundamental behavior. Each implementation of SMP2P must be able
to support a minimum of the current version and the previous version.
The feature flags represent any changes in SMP2P that are optional and
backwards compatible. Endpoints will negotiate the supported flag when the
SMEM items are created and they cannot be changed after negotiation has been
completed.
Negotiation Algorithm
----------------------
While creating the SMEM item the following algorithm shall be used.
if remote endpoint's SMEM Item exists
Read remote version number and flags
Local version number must be lower of
- remote version number
- highest supported local version number
Flags value is bitwise AND of
- remote feature flags
- locally supported flags
Create SMEM item and populate negotiated number and flags
Interrupt remote processor
if version and flags match, negotiation is complete, else wait
for remote interrupt below.
Else
Create SMEM item and populate it with highest supported version and any
requested feature flag.
Interrupt remote processor.
Wait for Interrupt below.
Upon receiving the interrupt from remote processor and negotiation is not
complete, check the version number and feature flags:
if equal, negotiation is complete.
if remote number is less than local number, and remote number is
supported:
Set local version number to remote version number
Bitwise AND local flags with remote flags
Interrupt remote processor
Negotiation is complete
if remote number is not supported, then negotiation has failed
Set version number to 0xFF and report failure in kernel log.
if remote number is more than local number:
Wait for remote endpoint to process our interrupt and negotiate down.
Creating an SMEM Entry
----------------------
Each new SMEM entry used in data transfer must be created at the end of the
entry array in the SMEM item and cannot be deleted until the system is
rebooted. The following sequence is be followed:
1) Compare Entries Valid and Entries Total to verify if there is room in the
entry array for this request (if not, return error code to client).
2) Populate the Identifier of new entry and do a write memory barrier.
3) Update Entries Valid and Entries Total and do a write memory barrier.
4) Interrupt remote endpoint.
Entry Write
-----------
An entry write is achieved by the following sequence of operations:
1) Update data field in the entry and do a write memory barrier.
2) Interrupt remote endpoint.
Entry Read / Receiving Interrupts
---------------------------------
An interrupt will be received from the remote system for one or more of the following events:
1) Initialization
2) Entry change
3) New Entry
As long as the SMEM item initialization is complete, then each interrupt should
trigger SMP2P to:
1) Compare valid entry data value to cached value and notify client if it
has changed.
2) Compare Entries Valid to cached value. If changed, initialize new entries.
Security
========
Since the implementation resides in the kernel and does not expose interfaces
to userspace, no security issues are anticipated. The usage of separate SMEM
items allows for future security enhancements in SMEM.
Performance
===========
No performance issues are anticipated as the signaling rate is expected to be
low and is performed in interrupt context which minimizes latency.
Interfaces
================
SMP2P is only supported in the kernel and interfaces with clients through the
GPIO and interrupt subsystems.
To map an entry to the client, the client must add two nodes to the Device
Tree:
1) A node that matches "qcom,smp2pgpio" to create the entry
2) A node that matches the client driver to provide the GPIO pin mapping
The details of the device tree entries for the GPIO interface are contained in
the file Documentation/devicetree/bindings/gpio/gpio-smp2p.txt.
/* SMP2P Test Driver for inbound entry. */
smp2pgpio_smp2p_7_in: qcom,smp2pgpio-smp2p-7-in {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <7>;
qcom,is-inbound;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/* SMP2P Test Client for inbound entry. */
qcom,smp2pgpio_test_smp2p_7_in {
compatible = "qcom,smp2pgpio_test_smp2p_7_in";
gpios = <&smp2pgpio_smp2p_7_in 0 0>,
<&smp2pgpio_smp2p_7_in 1 0>,
. . .
<&smp2pgpio_smp2p_7_in 31 0>;
};
/* SMP2P Test Driver for outbound entries */
smp2pgpio_smp2p_345_out: qcom,smp2pgpio-smp2p-7-out {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <7>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/* SMP2P Test Client for outbound entry. */
qcom,smp2pgpio_test_smp2p_7_out {
compatible = "qcom,smp2pgpio_test_smp2p_7_out";
gpios = <&smp2pgpio_smp2p_7_out 0 0>,
<&smp2pgpio_smp2p_7_out 1 0>,
. . .
<&smp2pgpio_smp2p_7_out 31 0>;
The client can use a match entry for "qcom,smp2pgpio_test_smp2p_7_in" to
retrieve the Device Tree configuration node. Once that node has been
retrieved, the client can call of_get_gpio() to get the virtual GPIO pin and
also use gpio_to_irq() to map the GPIO pin to a virtual interrupt. After that
point, the standard GPIO and Interrupt APIs can be used to manipulate the SMP2P
entries and receive notifications of changes. Examples of typical function
calls are shown below:
of_get_gpio()
gpio_get_value()
gpio_set_value()
gpio_to_irq()
request_irq()
free_irq()
Please reference the unit test code for example usage.
Subsystem Restart
=================
SMP2P is unaffected by SubSystem Restart (SSR) on the high-level OS side and is
actually used as an underlying communication mechanism for SSR. On the
peripheral system that is being restarted, SMP2P will zero out all existing
state entries upon reboot as part of the SMP2P initialization process and if the
SSR_ACK feature is enabled, then it waits for an acknowledgment as outlined in
the following subsections.
SSR_ACK Feature - Reboot Use Case (Non-HLOS Only)
-------------------------------------------------
If a remote system boots up after an SSR and sees that the remote and local
version numbers and feature flags are equal, then it zeros out entry values. If
the SSR_ACK feature is enabled, it will wait for an acknowledgment from the other
processor that it has seen the zero entry before completing the negotiation
sequence.
if remote and local version numbers and feature flags are equal
Zero out all entry values
if SSR_ACK feature is enabled
Set local RESTART_DONE flag to inverse of the remote RESTART_ACK
Send interrupt to remote system
Wait for interrupt and for remote RESTART_ACK to be equal to local
RESTART_DONE
Continue with normal negotiation sequence
Interrupt Use Case
------------------
For every interrupt triggered by a remote change, SMP2P will notify the client
of a change in state. In addition, if the SSR_ACK feature is enabled, the SSR
handshaking will also be handled.
if SSR_ACK feature is enabled
if remote RESTART_DONE != local RESTART_ACK
Notify client of entry change (will be * -> 0 transition)
Toggle local RESTART_ACK
Send interrupt to remote system
else
Notify client of entry change as usual
else
Notify client of entry change as usual
Debug
=====
The state values and names for all entries accessible by the Apps are
accessible through debugfs nodes for general debug purposes.
Debugfs entries for triggering unit-tests are also exported.
Internal logging will be performed using the IPC Logging module to enable
post-mortem analysis.
Testing
=======
On-target unit testing will be done to verify internal functionality and the
GPIO/IRQ API's.
Driver parameters
=================
One module parameter will be provided to change the verbosity of internal logging.
Config options
==============
Configuration of interrupts will be done using Device Tree per the format in
Documentation/devicetree/bindings/arm/msm/smp2p.txt. By default, the testing
components will be enabled since it does not affect performance and has a
minimal impact on kernel size. However, customers can disable the testing
component for size optimization.
CONFIG_MSM_SMP2P - enables SMP2P
CONFIG_MSM_SMP2P_TEST - enables unit test support
Dependencies
===========
Requires SMEM for creating the SMEM items.
User Space utilities
====================
No userspace utilities are planned.
Known issues
============
None.

28
Documentation/devicetree/bindings/arm/msm/bam_dmux.txt Normal file
View File

@ -0,0 +1,28 @@
Qualcomm Technologies, Inc. BAM Data Multiplexer Driver
Required properties:
- compatible : should be "qcom,bam_dmux"
- reg : the location and size of the BAM hardware
- interrupts : the BAM hardware to apps processor interrupt line
Optional properties:
-qcom,satellite-mode: the hardware needs to be configured in satellite mode
-qcom,rx-ring-size: the size of the receive ring buffer pool, default is 32
-qcom,max-rx-mtu: the maximum receive MTU that can be negotiated, in bytes.
Default is 2048. Other possible values are 4096, 8192, and 16384.
-qcom,no-cpu-affinity: boolean value indicating that workqueue CPU affinity
is not required.
-qcom,fast-shutdown: boolean value to support fast shutdown time.
Example:
qcom,bam_dmux@fc834000 {
compatible = "qcom,bam_dmux";
reg = <0xfc834000 0x7000>;
interrupts = <0 29 1>;
qcom,satellite-mode;
qcom,rx-ring-size = <64>;
qcom,max-rx-mtu = <8192>;
qcom,no-cpu-affinity;
qcom,fast-shutdown;
};

49
Documentation/devicetree/bindings/arm/msm/core_sleep_status.txt Normal file
View File

@ -0,0 +1,49 @@
* MSM Sleep status
MSM Sleep status device is used to check the power collapsed status of a
offlined core. The core that initiates the hotplug would wait on the
sleep status device before CPU_DEAD notifications are sent out. Some hardware
devices require that the offlined core is power collapsed before turning off
the resources that are used by the offlined core.
The required properties of core sleep status node are:
- compatible: qcom,cpu-sleep-status
The required properties of sleep status node are:
- reg: physical address of the sleep status register for the cpus
- qcom,cpu-sleep-status-mask - The bit mask within the status register that
indicates the Core's sleep state.
Example:
qcom,cpu-sleep-status {
compatible = "qcom,cpu-sleep-status";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
qcom,sleep-status = <&cpu0_slp_sts>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "qcom,kryo";
qcom,sleep-status = <&cpu1_slp_sts>;
};
};
cpu0_slp_sts: cpu-sleep-status@9981058 {
reg = <0x9981058 0x100>;
qcom,sleep-status-mask = <0xc00000>;
};
cpu1_slp_sts: cpu-sleep-status@9991058 {
reg = <0x9991058 0x100>;
qcom,sleep-status-mask = <0xc00000>;
}

27
Documentation/devicetree/bindings/arm/msm/ipc-spinlock.txt Normal file
View File

@ -0,0 +1,27 @@
Qualcomm Technologies, Inc. Interprocessor Communication Spinlock
--Dedicated Hardware Implementation--
Required properties:
- compatible : should be "qcom,ipc-spinlock-sfpb"
- reg : the location and size of the spinlock hardware
- qcom,num-locks : the number of locks supported
Example:
qcom,ipc-spinlock@fd484000 {
compatible = "qcom,ipc-spinlock-sfpb";
reg = <0xfd484000 0x1000>;
qcom,num-locks = <32>;
};
--LDREX Implementation--
Required properties:
- compatible : should be "qcom,ipc-spinlock-ldrex"
- reg : the location and size of the shared lock memory
Example:
qcom,ipc-spinlock@fa00000 {
compatible = "qcom,ipc-spinlock-ldrex";
reg = <0xfa00000 0x200000>;
};

22
Documentation/devicetree/bindings/arm/msm/jtag-fuse.txt Normal file
View File

@ -0,0 +1,22 @@
* JTAG-FUSE
The jtag-fuse entry specifies the memory mapped addresses for the fuse
registers. The jtag-fuse driver uses these to provide api(s) that can be used
by jtag save and restore driver(s) to query whether the Hardware they manage
is functionally disabled or not and take corresponding steps.
Required Properties:
compatible: component name used for driver matching, should be one of the
following:
"qcom,jtag-fuse" for jtag fuse device
"qcom,jtag-fuse-v2" for jtag fuse v2 device
"qcom,jtag-fuse-v3" for jtag fuse v3 device
reg: physical base address and length of the register set
reg-names: should be "fuse-base"
Example:
jtag_fuse: jtagfuse@fc4be024 {
compatible = "qcom,jtag-fuse";
reg = <0xfc4be024 0x8>;
reg-names = "fuse-base";
};

77
Documentation/devicetree/bindings/arm/msm/mpm.txt Normal file
View File

@ -0,0 +1,77 @@
* MSM Sleep Power Manager (mpm-v2)
The MPM acts a sleep power manager to shutdown the clock source and put the
device into a retention mode to save power. The MPM is also responsible for
waking up and bringing up the resources from sleep. The MPM driver configures
interrupts monitored by the MPM hardware before entering sleep through a
RPM interface.
The required nodes for the MPM driver are:
- compatible: "qcom, mpm-v2"
- reg: Specifies the base physical address(s) and the size of the MPM
registers. The MPM driver access two memory regions for confifure the
virtual MPM driver on the RPM. The first region is the memory space
shared with the virtual MPM driver. The second region is the address
to the register that triggers a interrupt to the RPM.
- reg-names: "vmpm" - string to identify the shared memory space region
"ipc" - string to identify the register that triggers a interrupt
- clocks: clock identifers used by clock driver while looking up mpm clocks.
- clock-names: name of the clock used by mpm driver.
- qcom,ipc-bit-offset: The bit to set in the ipc register that triggers a interrupt
to the RPM
- qcom,gic-parent: phandle to the gic interrupt controller
- qcom,gic-map: Provides a mapping of how a GIC interrupt is connect to a MPM. The
mapping is presented in tuples. Each tuple represents a MPM pin and
which GIC interrupt is routed to it. Since MPM monitors interrupts
only during system wide low power mode, system interrupts originating
from other processors can be ignored and assigned an MPM pin mapping
of 0xff.
- qcom,gpio-parent: phandle to the GPIO interrupt controller
- qcom,gpio-map: Provides a mapping of how a GPIO interrupt is connect to a MPM. The
mapping is presented in tuples. Each tuple represents a MPM pin and
which GIC interrupt is routed to it. Since MPM monitors interrupts
only during system wide low power mode, system interrupts originating
from other processors can be ignored and assigned an MPM pin mapping
of 0xff.
Optional Properties:
- qcom,num-mpm-irqs : Specifies the number of mpm interrupts supported on a
target. If the property isn't present, 64 interrupts are
considered for the target by default.
Example:
qcom,mpm@fc4281d0 {
compatible = "qcom,mpm-v2";
reg = <0xfc4281d0 0x1000>, /* MSM_RPM_MPM_BASE 4K*/
<0xfa006000 0x1000>; /* MSM_APCS_GCC_BASE 4K*/
reg-names = "vmpm", "ipc"
interrupts = <0 171 1>;
clocks = <&clock_rpm clk_xo_lpm_clk>;
clock-names = "xo";
qcom,ipc-bit-offset = <0>;
qcom,gic-parent = <&intc>;
qcom,gic-map = <25 132>,
<27 111>,
<0xff 48>,
<0xff 51>,
<0xff 52>,
<0xff 53>,
<0xff 54>,
<0xff 55>;
qcom,gpio-parent = <&msmgpio>;
qcom,gpio-map = <1 46>,
<2 150>,
<4 103>,
<5 104>,
<6 105>,
<7 106>,
<8 107>,
<53 37>,
<54 24>,
<55 14>;
};

3
Documentation/devicetree/bindings/arm/msm/msm.txt
View File

@ -22,6 +22,8 @@ restart@fc4ab000 {
* Compatible strings:
SoCs:
- MDM9607
compatible = "qcom,mdm9607"
- APQ8016
compatible = "qcom,apq8016"
@ -244,3 +246,4 @@ compatible = "qcom,atollp-atp"
compatible = "qcom,atollp-qrd"
compatible = "qcom,qcs610-iot"
compatible = "qcom,qcs410-iot"
compatible = "qcom,mdm9607-mtp"

16
Documentation/devicetree/bindings/arm/msm/msm_ipc_router.txt Normal file
View File

@ -0,0 +1,16 @@
Qualcomm Technologies, Inc. IPC Router
Required properties:
-compatible: should be "qcom,ipc_router"
-qcom,node-id: unique ID to identify the node in network
Optional properties:
-qcom,default-peripheral: String property to indicate the default peripheral
to communicate
Example:
qcom,ipc_router {
compatible = "qcom,ipc_router";
qcom,node-id = <1>;
qcom,default-peripheral = "modem";
};

34
Documentation/devicetree/bindings/arm/msm/msm_ipc_router_smd_xprt.txt Normal file
View File

@ -0,0 +1,34 @@
Qualcomm Technologies, Inc. IPC Router SMD Transport
Required properties:
-compatible: should be "qcom,ipc_router_smd_xprt"
-qcom,ch-name: the SMD channel name used by the SMD transport
-qcom,xprt-remote: string that defines the edge of the transport (PIL Name)
-qcom,xprt-linkid: unique integer to identify the tier to which the link
belongs to in the network and is used to avoid the
routing loops while forwarding the broadcast messages
-qcom,xprt-version: unique version ID used by SMD transport header
Optional properties:
-qcom,fragmented-data: Indicate the SMD transport supports fragmented data
-qcom,disable-pil-loading: Disable PIL Loading of the remote subsystem
Example:
qcom,ipc_router_modem_xprt {
compatible = "qcom,ipc_router_smd_xprt";
qcom,ch-name = "IPCRTR";
qcom,xprt-remote = "modem";
qcom,xprt-linkid = <1>;
qcom,xprt-version = <1>;
qcom,fragmented-data;
qcom,disable-pil-loading;
};
qcom,ipc_router_q6_xprt {
compatible = "qcom,ipc_router_smd_xprt";
qcom,ch-name = "IPCRTR";
qcom,xprt-remote = "adsp";
qcom,xprt-linkid = <1>;
qcom,xprt-version = <1>;
qcom,fragmented-data;
};

448
Documentation/devicetree/bindings/arm/msm/msm_thermal.txt Normal file
View File

@ -0,0 +1,448 @@
MSM thermal driver (MSM_THERMAL)
MSM_THERMAL is a kernel platform driver which regulates thermal conditions
on the device during kernel boot. The goal of MSM_THERMAL is to prevent the
temperature of the system from exceeding a thermal limit at which it cannot
operate. Examples are CPU junction thermal limit, or POP memory thermal limit.
The MSM_THERMAL driver polls the TSENS sensor hardware during boot, and
reduces the maximum CPU frequency allowed in steps, to limit power/thermal
output when a threshold temperature is crossed. It restores the maximum CPU
frequency allowed in the same stepwise fashion when the threshold temperature
(with hysteresis gap) is cleared.
The devicetree representation of the MSM_THERMAL block should be:
Required properties
- compatible: "qcom,msm-thermal"
- qcom,sensor-id: The id of the TSENS sensor polled for temperature.
Typically the sensor closest to CPU0.
- qcom,poll-ms: Sampling interval to read sensor, in ms.
- qcom,limit-temp: Threshold temperature to start stepping CPU down, in degC.
- qcom,temp-hysteresis: Degrees C below threshold temperature to step CPU up.
- qcom,freq-step: Number of frequency steps to take on each CPU mitigation.
Optional properties
- reg: Physical address for uio mapping
- qcom,core-limit-temp: Threshold temperature to start shutting down cores
in degC
- qcom,core-temp-hysteresis: Degrees C below which the cores will be brought
online in sequence.
- qcom,hotplug-temp: Threshold temperature to start shutting down cores
in degC. This will be used when polling based
core control is disabled. The difference between hotplug-temp
and core-limit-temp is that core-limit-temp is used during
early boot prior to thermal_sys being available for hotplug.
- qcom,hotplug-temp-hysteresis: Degrees C below which thermal will not force the
cores to be offlined. Cores can be brought online if needed.
- qcom,freq-mitigation-temp: Threshold temperature to mitigate
the CPU max frequency in degC. This will be
used when polling based frequency control is disabled.
The difference between freq-mitigation-temp
and limit-temp is that limit-temp is used during
early boot prior to thermal_sys being available for registering
temperature thresholds. Also, this emergency frequency
mitigation is a single step frequency mitigation to a predefined value
as opposed to the step by step frequency mitigation during boot-up.
- qcom,freq-mitigation-temp-hysteresis: Degrees C below which thermal will not mitigate the
cpu max frequency.
- qcom,freq-mitigation-value: The frequency value (in kHz) to which the thermal
should mitigate the CPU, when the freq-mitigation-temp
threshold is reached.
- qcom,vdd-restriction-temp: When temperature is below this threshold, will
enable vdd restriction which will set higher voltage on
key voltage rails, in degC.
- qcom,vdd-restriction-temp-hysteresis: When temperature is above this threshold
will disable vdd restriction on key rails, in degC.
- qcom,pmic-sw-mode-temp: Threshold temperature to disable auto mode on the
rail, in degC. If this property exists,
qcom,pmic-sw-mode-temp-hysteresis and
qcom,pmic-sw-mode-regs need to exist, otherwise return error.
- qcom,pmic-sw-mode-temp-hysteresis: Degree below threshold temperature to
enable auto mode on the rail, in degC. If this property exists,
qcom,pmic-sw-mode-temp and qcom,pmic-sw-mode-regs need to
exist, otherwise return error.
- qcom,pmic-sw-mode-regs: Array of the regulator names that will want to
disable/enable automode based on the threshold. If this
property exists, qcom,pmic-sw-mode-temp and
qcom,pmic-sw-mode-temp-hysteresis need to exist, otherwise
return error. Also, if this property is defined, will have to
define <consumer_supply_name>-supply = <&phandle_of_regulator>
- <consumer_supply_name>-supply = <&phandle_of_regulator>: consumer_supply_name
is the name that's defined in thermal driver.
phandle_of_regulator is defined by reuglator device tree.
- qcom,online-hotplug-core: This property should be defined in targets where
KTM should online cores, which are hotplugged due to
thermal condition.
- qcom,synchronous-cluster-id: This property specifies an array of synchronous cluster-ID's.
This property will be used by KTM to optimize the synchronous
cluster frequency update.
- qcom,synchronous-cluster-map: This property specifies an array of cluster-ID,
number of cpus in that cluster and their corresponding cpu
phandles. This property should be defined in targets where
the kernel topology module is not present.
In the older kernel version, where the kernel topology module is
not available, KTM gets the mapping information from this property.
- qcom,disable-vdd-mx: If this property is defined, the feature VDD MX
restriction will be disabled. All other properties
corresponding to this feature will be ignored.
- qcom,disable-vdd-rstr: If this property is defined, the feature VDD
restriction will be disabled. All other properties
corresponding to this feature will be ignored.
- qcom,disable-sensor-info: If this property is defined, the feature sensor
alias info will be disabled. All other properties
corresponding to this feature will be ignored.
- qcom,disable-ocr: If this property is defined, the feature optimum current
request will be disabled. All other properties
corresponding to this feature will be ignored.
- qcom,disable-psm: If this property is defined, the feature PMIC software
mode will be disabled. All other properties
corresponding to this feature will be ignored.
- qcom,disable-gfx-phase-ctrl: If this property is defined, the feature graphics
phase control will be disabled. All other properties
corresponding to this feature will be ignored.
- qcom,disable-cx-phase-ctrl: If this property is defined, the feature
cx phase control will be disabled. All other properties
corresponding to this feature will be ignored.
- qcom,therm-ddr-lm-info: If this optional property is defined, it enables
DDR frequency restriction feature. It expects array of
sensor id to be monitored, high threshold and low threshold
for that sensor respectively.
Optional child nodes
- qcom,pmic-opt-curr-temp: Threshold temperature for requesting optimum current (request
dual phase) for rails with PMIC, in degC. If this property exists,
then the properties, qcom,pmic-opt-curr-temp-hysteresis and
qcom,pmic-opt-curr-regs should also be defined to enable this
feature.
- qcom,pmic-opt-curr-temp-hysteresis: Degree below the threshold to disable the optimum
current request for a rail, in degC. If this property exists,
then the properties, qcom,pmic-opt-curr-temp and
qcom,pmic-opt-curr-regs should also be defined to enable
this feature.
- qcom,pmic-opt-curr-regs: Name of the rails for which the optimum current should be
requested. If this property exists, then the properties,
qcom,pmic-opt-curr-temp and qcom,pmic-opt-curr-temp-hysteresis
should also be defined to enable this feature.
- qcom,pmic-opt-curr-sensor-id: Sensor, which needs to be monitored for requesting OCR
when qcom,pmic-opt-curr-temp threshold is reached.
It is an optional property, if it is configured, msm_thermal will
monitor only this sensor, otherwise it will monitor all TSENS for
this feature. If this property exists, then the properties,
qcom,pmic-opt-curr-temp, qcom,pmic-opt-curr-temp-hysteresis and
qcom,pmic-opt-curr-regs should also be defined to enable this feature.
- qcom,<vdd restriction child node name>: Define the name of the child node.
If this property exisits, qcom,vdd-rstr-reg, qcom,levels
need to exist. qcom,min-level is optional if qcom,freq-req
exists, otherwise it's required.
- qcom,vdd-rstr-reg: Name of the rail
- qcom,levels: Array of the level values. Unit is corner voltage for voltage request
or kHz for frequency request.
- qcom,min-level: Request this level as minimum level when disabling voltage
restriction. Unit is corner voltage for voltage request.
This will not be required if qcom,freq-req exists.
- qcom,freq-req: Flag to determine if we should restrict frequency on this rail
instead of voltage.
- qcom,max-freq-level: Request this frequency as scaling maximum level when
enabling vdd restriction feature for a rail. This is
an optional property which is only applicable to the rail
with "qcom,freq-req" property set.
- qcom,cx-phase-hot-crit-temp: Threshold temperature for sending the 'HOT_CRITICAL'
temperature band to RPM, in degC. This will aid RPM
in deciding the number of phases required for CX rail.
If this property exists, then the property,
qcom,cx-phase-hot-crit-temp-hyst should also be defined to
enable this feature.
- qcom,cx-phase-hot-crit-temp-hyst: Degree below the threshold to send the 'WARM'
temperature band to RPM, in degC. This will aid RPM
in deciding the number of phases required for CX.
If this property exists, then the property,
qcom,cx-phase-hot-crit-temp should also be defined to enable
this feature.
- qcom,cx-phase-resource-key: The key name to be used for sending the CX
temperature band message to RPM. This property should
be defined along with the other properties required for
CX phase selection feature.
- qcom,gfx-phase-hot-crit-temp: Threshold temperature for sending the 'HOT_CRITICAL'
temperature band to RPM, in degC. This will aid RPM in
deciding the number of phases required for GFX rail.
If this property exists, then the properties,
qcom,gfx-phase-hot-crit-temp-hyst and qcom,gfx-sensor-id
should also be defined to enable this feature.
- qcom,gfx-phase-hot-crit-temp-hyst: Degree below the threshold to clear the 'HOT_CRITICAL'
band and send the 'WARM' temperature band to RPM, in degC.
This will aid RPM in deciding the number of phases required
for GFX rail. If this property exists, then the properties,
qcom,gfx-phase-hot-crit-temp and qcom,gfx-sensor-id
should also be defined to enable this feature.
- qcom,gfx-phase-warm-temp: Threshold temperature for sending the 'WARM' temperature
band to RPM, in degC. This will aid RPM in deciding the
number of phases required for GFX rail. If this property
exists, then the properties, qcom,gfx-sensor-id and
qcom,gfx-phase-warm-temp-hyst should also be defined to
enable this feature.
- qcom,gfx-phase-warm-temp-hyst: Degree below the threshold to clear the 'WARM'
band and send the 'NORMAL' temperature band to RPM, in degC.
This will aid RPM in deciding the number of phases required
for GFX rail. If this property exists, then the property,
qcom,gfx-sensor-id and qcom,gfx-phase-warm-temp should also
be defined to enable this feature.
-qcom,gfx-sensor-id: The ID of the TSENS sensor, which is closest to graphics
processor, monitoring the GPU temperature. If this property
exists, then the property, qcom,gfx-phase-hot-crit-temp and
qcom,gfx-phase-hot-crit-temp-hyst or/and qcom,gfx-phase-warm-temp
and qcom,gfx-phase-warm-temp-hyst should also be defined to
enable this feature.
- qcom,gfx-phase-resource-key: The key name to be used for sending the GFX temperature
band message to RPM. This property should be defined along
with the other properties required for GFX phase selection
feature.
- qcom,rpm-phase-resource-type: The RPM resource type name to be used for sending
temperature bands for CX and GFX phase selection. This
property should be defined along with the other properties
required for CX and GFX phase selection feature.
- qcom,rpm-phase-resource-id: The RPM resource ID to be used for sending temperature
bands for CX and GFX phase selection. This property should
be defined along with the other properties required for CX
and GFX phase selection feature.
- qcom,mx-restriction-temp: Threshold temperature below which the module votes for
higher data retention voltage of MX and CX supply. If and only if this
property exists, then the property qcom,mx-restriction-temp-hysteresis,
qcom,mx-retention-min should also be present. Also, if this
property is defined, will have to define vdd-mx-supply =
<&phandle_of_regulator>
- qcom,mx-restriction-temp-hysteresis: Degree above the threshold to remove MX and CX vote.
If this property exists, then the property qcom,mx-restriction-temp,
qcom,mx-retention-min should also be present.Also, if this
property is defined, will have to define vdd-mx-supply =
<&phandle_of_regulator>
- qcom,mx-retention-min: Minimum data retention voltage to be applied to MX rail if
the low threshold is crossed. If this property exists, then the
property qcom,mx-restriction-temp and
qcom,mx-restriction-temp-hysteresis should also be present.
Also, if this property is defined, will have to define
vdd-mx-supply = <&phandle_of_regulator>
- qcom,cx-retention-min: Minimum data retention voltage to be applied to CX rail if the low
threshold is crossed. If this property exists, then the property
qcom,mx-restriction-temp and qcom,mx-restriction-temp-hysteresis
should also be present. Also, if this property is defined, will
have to define vdd-cx-supply = <&phandle_of_regulator>.
- qcom,mx-restriction-sensor_id: sensor id, which needs to be monitored for requesting MX/CX
retention voltage. If this optional property is defined, msm_thermal
will monitor only this sensor, otherwise by default it will monitor
all TSENS for this feature. If this property exists, then the properties,
qcom,mx-restriction-temp, qcom,mx-restriction-temp-hysteresis and
qcom,mx-retention-min should also be defined to enable this feature.
- qcom,therm-reset-temp: Degree above which the KTM will initiate a secure watchdog reset.
When this property is defined, KTM will monitor all the tsens from
boot time and will initiate a secure watchdog reset if any of the
tsens temperature reaches this threshold. This reset helps in
generating more informative crash dumps opposed to the crash dump
generated by the hardware reset.
Example:
qcom,msm-thermal {
compatible = "qcom,msm-thermal";
reg = <0x70000 0x1000>;
qcom,sensor-id = <0>;
qcom,poll-ms = <250>;
qcom,limit-temp = <60>;
qcom,temp-hysteresis = <10>;
qcom,freq-step = <2>;
qcom,therm-reset-temp = <115>;
qcom,core-limit-temp = <90>;
qcom,core-temp-hysteresis = <10>;
qcom,hotplug-temp = <110>;
qcom,hotplug-temp-hysteresis = <20>;
qcom,freq-mitigation-temp = <110>;
qcom,freq-mitigation-temp-hysteresis = <20>;
qcom,freq-mitigation-value = <960000>;
qcom,rpm-phase-resource-type = "misc";
qcom,rpm-phase-resource-id = <0>;
qcom,cx-phase-resource-key = "tmpc";
qcom,cx-phase-hot-crit-temp = <75>;
qcom,cx-phase-hot-crit-temp-hyst = <15>;
qcom,gfx-phase-warm-temp = <60>;
qcom,gfx-phase-warm-temp-hyst = <10>;
qcom,gfx-phase-hot-crit-temp = <85>;
qcom,gfx-phase-hot-crit-temp-hyst = <15>;
qcom,gfx-sensor-id = <4>;
qcom,gfx-phase-resource-key = "tmpg";
qcom,pmic-sw-mode-temp = <90>;
qcom,pmic-sw-mode-temp-hysteresis = <80>;
qcom,pmic-sw-mode-regs = "vdd-dig";
qcom,vdd-restriction-temp = <5>;
qcom,vdd-restriction-temp-hysteresis = <10>;
vdd-dig-supply=<&pm8841_s2_floor_corner>
qcom,mx-restriction-temp = <5>;
qcom,mx-restriction-temp-hysteresis = <10>;
qcom,mx-retention-min = <710000>;
qcom,mx-restriction-sensor_id = <2>;
vdd-mx-supply = <&pma8084_s1>;
qcom,cx-retention-min = <RPM_SMD_REGULATOR_LEVEL_RETENTION_PLUS>;
vdd-cx-supply = <&pmd9635_s5_level>;
qcom,online-hotplug-core;
qcom,therm-ddr-lm-info = <1 90 75>;
qcom,synchronous-cluster-id = <0 1>; /* Indicates cluster 0 and 1 are synchronous */
qcom,synchronous-cluster-map = <0 2 &CPU0 &CPU1>,
<1 2 &CPU2 &CPU3>;
/* <cluster-ID, number of cores in cluster, cpu phandles>.
** In the above case, the cluster with ID 0 & 1 has 2 cores
** and their phandles are mentioned.
*/
qcom,vdd-dig-rstr{
qcom,vdd-rstr-reg = "vdd-dig";
qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */
qcom,min-level = <1>; /* No Request */
};
qcom,vdd-apps-rstr{
qcom,vdd-rstr-reg = "vdd-apps";
qcom,levels = <1881600 1958400 2265600>;
qcom,freq-req;
qcom,max-freq-level = <1958400>;
};
};
The sensor information node is an optional node that holds information
about thermal sensors on a target. The information includes sensor type,
sensor name, sensor alias and sensor scaling factor. The parent node
name is qcom,sensor-information. It has a list of optional child
nodes, each representing a sensor. The child node is named as
qcom,sensor-information-<id>. The id takes values sequentially
from 0 to N-1 where N is the number of sensors. This id doesn't
relate to zone id or sensor id.
The devicetree representation of sensor information node should be:
1.0 Required properties:
- compatible: "qcom,sensor-information"
1.1 Optional nodes:
qcom,sensor-information-<id>
The below properties belong to the child node qcom,sensor-information-<id>.
Following are the required and optional properties of a child node.
1.1.a Required properties:
- qcom,sensor-type: Type of a sensor. A sensor can be of type tsens,
alarm or adc.
tsens: Sensors that are on MSM die.
alarm: Sensors that are on PMIC die.
adc: Sensors that are usually thermistors
placed out of the die.
- qcom,sensor-name: Name of a sensor as defined by low level sensor driver.
1.1.b Optional properties:
- qcom,alias-name: Alias name for a sensor. The alias name corresponds
to a device such as gpu/pop-mem whose temperature
is relative to the sensor temperature defined in the
child node. This node can not be used for providing
alias name for cpu devices. Thermal driver assigns the
cpu device alias, based on the sensor defined in the
cpu mitigation profile.
- qcom,scaling-factor: The unit that needs to be multiplied to the
sensor temperature to get temperature unit in
degree centigrade. If this property is not
present, a default scaling factor of 1 is assigned
to a sensor.
Example:
qcom,sensor-information {
compatible = "qcom,sensor-information";
sensor_information0: qcom,sensor-information-0 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor0";
};
sensor_information1: qcom,sensor-information-1 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor1";
};
sensor_information2: qcom,sensor-information-2 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor2";
};
sensor_information3: qcom,sensor-information-3 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor3";
};
sensor_information4: qcom,sensor-information-4 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor4";
};
sensor_information5: qcom,sensor-information-5 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor5";
};
sensor_information6: qcom,sensor-information-6 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor6";
qcom,alias-name = "cpu7";
}
sensor_information7: qcom,sensor-information-7 {
qcom,sensor-type = "alarm";
qcom,sensor-name = "pm8994_tz";
qcom,scaling-factor = <1000>;
};
};
===============================================================================
Mitigation Profile:
===============================================================================
Thermal driver allows users to specify various mitigation profiles and
associate a profile to a device. The device should have a phandle, to associate
itself with a mitigation profile, using a "qcom,limits-info" property.
This profile can specify whether to mitigate the device during various
limiting conditions.
Required Node:
- qcom,limit_info-#: This is a mitigation profile node. A profile should
normally have a sensor(s) to monitor and a list
of properties enabling or disabling a mitigation.
Required properties:
- qcom,temperature-sensor: Array of phandle(s) to the temperature sensor(s) that
need(s) to be used for monitoring the device associated
with this mitigation profile. Right now the first
sensor will be used for KTM CPU monitoring. Alias
name of multiple sensors monitoring a same device will
be differentiated by appending an index like, "cpu0_0"
and "cpu0_1". A single sensor monitoring multiple
devices will have an alias name like "cpu0-cpu1-cpu2".
Optional properties:
- qcom,boot-frequency-mitigate: Enable thermal frequency mitigation
during boot.
- qcom,emergency-frequency-mitigate: Enable emergency frequency mitigation.
- qcom,hotplug-mitigation-enable: Enable hotplug mitigation. This enables
hotplug mitigation both during boot and emergency
condition.
Example:
mitigation_profile7: qcom,limit_info-7 {
qcom,temperature-sensor =
<&sensor_information6 &sensor_information8>;
qcom,boot-frequency-mitigate;
qcom,emergency-frequency-mitigate;
qcom,hotplug-mitigation-enable;
};

16
Documentation/devicetree/bindings/arm/msm/rdbg-smp2p.txt
View File

@ -13,3 +13,19 @@ Example:
qcom,smp2p_interrupt_rdbg_2_in {
compatible = "qcom,smp2p-interrupt-rdbg-2-in";
};
Required properties:
-compatible : Should be one of
To communicate with modem
qcom,smp2pgpio_client_rdbg_2_in (inbound)
qcom,smp2pgpio_client_rdbg_2_out (outbound)
To communicate with modem
qcom,smp2pgpio_client_rdbg_1_in (inbound)
qcom,smp2pgpio_client_rdbg_1_out (outbound)
-gpios : the relevant gpio pins of the entry.
Example:
qcom,smp2pgpio_client_rdbg_2_in {
compatible = "qcom,smp2pgpio_client_rdbg_2_in";
gpios = <&smp2pgpio_rdbg_2_in 0 0>;
};

61
Documentation/devicetree/bindings/arm/msm/rpm-log.txt Normal file
View File

@ -0,0 +1,61 @@
* RPM Log
RPM maintains Ulog in the RPM RAM. A device tree node is added
that will hold the address of the RPM RAM region from where
Ulog is read. The physical address from the RPM RAM region
contains a header where various parameters to read the log are
defined. These parameter's offsets in the header are also stored
as a part of the device tree node.
The required properties for rpm-log are:
- compatible: "qcom,rpm-log"
- reg: Specifies the base physical address and the size of the RPM
registers from where ulog is read.
Second register(optional) specifies the offset of the rpm
log start address pointer. If the second register is available,
the offset value read is added to the first register address
to read the ulog message.
- qcom,rpm-addr-phys: RPM reads physical address of the RPM RAM region
differently when compared to Apps. Physical address of
the RPM RAM region is at an offset when seen from Apps.
This property specifies the offset which will get added
to the physical address of RPM RAM to make it
accessible to the Apps.
- qcom,offset-version: Offset from the start of the phys_addr_base where version
information is stored.
- qcom,offset-page-buffer-addr: Offset from the start of the phys_addr_base
where raw log start address is stored. Raw log
start address is the start of raw log in the
RPM address space as it should be seen from rpm.
- qcom,offset-log-len: Offset from the start of the phy_addr_base where log
length is stored.
- qcom,offset-log-len-mask: Offset from the start of the phy_addr_base where
log length mask is stored.
- qcom,offset-page-indices: Offset from the start of the phy_addr_base where
index to the writer is stored.
Example 1:
qcom,rpm-log@fc19dc00 {
compatible = "qcom,rpm-log";
reg = <0xfc19dc00 0x2000>;
qcom,offset-rpm-addr = <0xfc000000>;
qcom,offset-version = <4>;
qcom,offset-page-buffer-addr = <36>;
qcom,offset-log-len = <40>;
qcom,offset-log-len-mask = <44>;
qcom,offset-page-indices = <56>;
};
Example 2:
qcom,rpm-log@fc000000 {
compatible = "qcom,rpm-log";
reg = <0xfc000000 0x2000>,
<0xfc190018 0x4>;
qcom,offset-rpm-addr = <0xfc000000>;
qcom,offset-version = <4>;
qcom,offset-page-buffer-addr = <36>;
qcom,offset-log-len = <40>;
qcom,offset-log-len-mask = <44>;
qcom,offset-page-indices = <56>;
};

26
Documentation/devicetree/bindings/arm/msm/rpm-rbcpr-stats.txt Normal file
View File

@ -0,0 +1,26 @@
* RPM RBCPR
The RBCPR(Rapid Bridge Core Power Reduction) is module on RPM that controls
the voltage level on the chip based on feedback received through various
sensors on the chip that allow compensation of the chip process variation,
temperature etc.
RPM maintains RBCPR (Rapid Bridge Core Power Reduction) related stats in
data memory. This module allows users to read those stats.
The required properties for rpm-stats are:
- compatible: "qcom,rpmrbcpr-stats"
- reg: Pointer to the start of the RPM Data Memory. The size of the memory
is inclusive of the entire RPM data memory.
- qcom,start_offset: The offset at which the RBCPR stats are maintained. The
driver module reads this parameter to get another offset
that contain the rbcpr stats.
Example:
qcom,rpm-rbcpr-stats@fc000000 {
compatible = "qcom,rpmrbcpr-stats";
reg = <0xfc000000 0x1a0000>;
qcom,start-offset = <0x190010>;
};

12
Documentation/devicetree/bindings/arm/msm/sleepstate-smp2p.txt
View File

@ -17,3 +17,15 @@ qcom,smp2p_sleepstate {
interrupts = <0 0>;
interrupt-names = "smp2p-sleepstate-in";
};
Required properties:
-compatible : should be "qcom,smp2pgpio_sleepstate_3_out";
-gpios : the relevant gpio pins of the entry.
Example:
qcom,smp2pgpio-sleepstate-3-out {
compatible = "qcom,smp2pgpio_sleepstate_3_out";
gpios = <&smp2pgpio_sleepstate_3_out 0 0>;
};

42
Documentation/devicetree/bindings/arm/msm/smdpkt.txt Normal file
View File

@ -0,0 +1,42 @@
Qualcomm Technologies, Inc. Shared Memory Packet Driver (smdpkt)
[Root level node]
Required properties:
-compatible : should be "qcom,smdpkt"
[Second level nodes]
qcom,smdpkt-port-names
Required properties:
-qcom,smdpkt-remote : the remote subsystem name
-qcom,smdpkt-port-name : the smd channel name
-qcom,smdpkt-dev-name : the smdpkt device name
Example:
qcom,smdpkt {
compatible = "qcom,smdpkt";
qcom,smdpkt-data5-cntl {
qcom,smdpkt-remote = "modem";
qcom,smdpkt-port-name = "DATA5_CNTL";
qcom,smdpkt-dev-name = "smdcntl0";
};
qcom,smdpkt-data6-cntl {
qcom,smdpkt-remote = "modem";
qcom,smdpkt-port-name = "DATA6_CNTL";
qcom,smdpkt-dev-name = "smdcntl1";
};
qcom,smdpkt-cxm-qmi-port-8064 {
qcom,smdpkt-remote = "wcnss";
qcom,smdpkt-port-name = "CXM_QMI_PORT_8064";
qcom,smdpkt-dev-name = "smd_cxm_qmi";
};
qcom,smdpkt-loopback {
qcom,smdpkt-remote = "modem";
qcom,smdpkt-port-name = "LOOPBACK";
qcom,smdpkt-dev-name = "smd_pkt_loopback";
};
};

39
Documentation/devicetree/bindings/arm/msm/smdtty.txt Normal file
View File

@ -0,0 +1,39 @@
Qualcomm Technologies, Inc. Shared Memory TTY Driver (smdtty)
[Root level node]
Required properties:
-compatible : should be "qcom,smdtty"
[Second level nodes]
qcom,smdtty-port-names
Required properties:
-qcom,smdtty-remote: the remote subsystem name
-qcom,smdtty-port-name : the smd channel name
Optional properties:
-qcom,smdtty-dev-name : the smdtty device name
Required alias:
- The index into TTY subsystem is specified via an alias with the following format
'smd{n}' where n is the tty device index.
Example:
aliases {
smd1 = &smdtty_apps_fm;
smd36 = &smdtty_loopback;
};
qcom,smdtty {
compatible = "qcom,smdtty";
smdtty_apps_fm: qcom,smdtty-apps-fm {
qcom,smdtty-remote = "wcnss";
qcom,smdtty-port-name = "APPS_FM";
};
smdtty_loopback: smdtty-loopback {
qcom,smdtty-remote = "modem";
qcom,smdtty-port-name = "LOOPBACK";
qcom,smdtty-dev-name = "LOOPBACK_TTY";
};
};

435
Documentation/devicetree/bindings/coresight/coresight.txt Normal file
View File

@ -0,0 +1,435 @@
* CoreSight Components
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suite a particular
SoCs tracing needs. These trace components can generally be classified as sinks,
links and sources. Trace data produced by one or more sources flows through the
intermediate links connecting the source to the currently selected sink. Each
CoreSight component device should use these properties to describe its hardware
characteristcs.
Required properties:
- compatible : name of the component used for driver matching, should be one of
the following:
"arm,coresight-tmc" for coresight tmc-etr or tmc-etf device,
"arm,coresight-tpiu" for coresight tpiu device,
"qcom,coresight-replicator" for coresight replicator device,
"arm,coresight-funnel" for coresight funnel devices,
"qcom,coresight-tpda" for coresight tpda device,
"qcom,coresight-tpdm" for coresight tpdm device,
"qcom,coresight-dbgui" for coresight dbgui device
"arm,coresight-stm" for coresight stm trace device,
"arm,coresight-etm" for coresight etm trace devices,
"arm,coresight-etmv4" for coresight etmv4 trace devices,
"qcom,coresight-csr" for coresight csr device,
"arm,coresight-cti" for coresight cti devices,
"qcom,coresight-hwevent" for coresight hardware event devices
"arm,coresight-fuse" for coresight fuse v1 device,
"arm,coresight-fuse-v2" for coresight fuse v2 device,
"arm,coresight-fuse-v3" for coresight fuse v3 device,
"qcom,coresight-remote-etm" for coresight remote processor etm trace device,
"qcom,coresight-qpdi" for coresight qpdi device
- reg : physical base address and length of the register set(s) of the component.
Not required for the following compatible string:
- "qcom,coresight-remote-etm"
- reg-names : names corresponding to each reg property value.
Not required for the following compatible string:
- "qcom,coresight-remote-etm"
The reg-names that need to be used with corresponding compatible string
for a coresight device are:
- for coresight tmc-etr or tmc-etf device:
compatible : should be "arm,coresight-tmc"
reg-names : should be:
"tmc-base" - physical base address of tmc configuration
registers
"bam-base" - physical base address of tmc-etr bam registers
- for coresight tpiu device:
compatible : should be "arm,coresight-tpiu"
reg-names : should be:
"tpiu-base" - physical base address of tpiu registers
- for coresight replicator device
compatible : should be "qcom,coresight-replicator"
reg-names : should be:
"replicator-base" - physical base address of replicator
registers
- for coresight funnel devices
compatible : should be "arm,coresight-funnel"
reg-names : should be:
"funnel-base" - physical base address of funnel registers
- for coresight tpda trace device
compatible : should be "qcom,coresight-tpda"
reg-names : should be:
"tpda-base" - physical base address of tpda registers
- for coresight tpdm trace device
compatible : should be "qcom,coresight-tpdm"
reg-names : should be:
"tpdm-base" - physical base address of tpdm registers
- for coresight dbgui device:
compatible : should be "qcom,coresight-dbgui"
reg-names : should be:
"dbgui-base" - physical base address of dbgui registers
- for coresight stm trace device
compatible : should be "arm,coresight-stm"
reg-names : should be:
"stm-base" - physical base address of stm configuration
registers
"stm-data-base" - physical base address of stm data registers
- for coresight etm trace devices
compatible : should be "arm,coresight-etm"
reg-names : should be:
"etm-base" - physical base address of etm registers
- for coresight etmv4 trace devices
compatible : should be "arm,coresight-etmv4"
reg-names : should be:
"etm-base" - physical base address of etmv4 registers
- for coresight csr device:
compatible : should be "qcom,coresight-csr"
reg-names : should be:
"csr-base" - physical base address of csr registers
- for coresight cti devices:
compatible : should be "arm,coresight-cti"
reg-names : should be:
"cti<num>-base" - physical base address of cti registers
- for coresight hardware event devices:
compatible : should be "qcom,coresight-hwevent"
reg-names : should be:
"<ss-mux>" - physical base address of hardware event mux
control registers where <ss-mux> is subsystem mux it
represents
- for coresight fuse device:
compatible : should be "arm,coresight-fuse"
reg-names : should be:
"fuse-base" - physical base address of fuse registers
"nidnt-fuse-base" - physical base address of nidnt fuse registers
"qpdi-fuse-base" - physical base address of qpdi fuse registers
- for coresight qpdi device:
compatible : should be "qcom,coresight-qpdi"
reg-names : should be:
"qpdi-base" - physical base address of qpdi registers
- coresight-id : unique integer identifier for the component
- coresight-name : unique descriptive name of the component
- coresight-nr-inports : number of input ports on the component
Optional properties:
- coresight-outports : list of output port numbers of this component
- coresight-child-list : list of phandles pointing to the children of this
component
- coresight-child-ports : list of input port numbers of the children
- coresight-default-sink : represents the default compile time CoreSight sink
- coresight-ctis : list of ctis that this component interacts with
- qcom,cti-save : boolean, indicating cti context needs to be saved and restored
- qcom,cti-hwclk : boolean, indicating support of hardware clock to access cti
registers to be saved and restored
- qcom,cti-gpio-trigin : cti trigger input driven by gpio
- qcom,cti-gpio-trigout : cti trigger output sent to gpio
- qcom,pc-save : program counter save implemented
- qcom,blk-size : block size for tmc-etr to usb transfers
- qcom,memory-size : size of coherent memory to be allocated for tmc-etr buffer
- qcom,round-robin : indicates if per core etms are allowed round-robin access
by the funnel
- qcom,write-64bit : only 64bit data writes supported by stm
- qcom,data-barrier : barrier required for every stm data write to channel space
- <supply-name>-supply: phandle to the regulator device tree node. The required
<supply-name> is "vdd" for SD card and "vdd-io" for SD
I/O supply. Used for tpiu component
- qcom,<supply>-voltage-level : specifies voltage level for vdd supply. Should
be specified in pairs (min, max) with units
being uV. Here <supply> can be "vdd" for SD card
vdd supply or "vdd-io" for SD I/O vdd supply.
- qcom,<supply>-current-level : specifies current load levels for vdd supply.
Should be specified in pairs (lpm, hpm) with
units being uA. Here <supply> can be "vdd" for
SD card vdd supply or "vdd-io" for SD I/O vdd
supply.
- qcom,hwevent-clks : list of clocks required by hardware event driver
- qcom,hwevent-regs : list of regulators required by hardware event driver
- qcom,byte-cntr-absent : specifies if the byte counter feature is absent on
the device. Only relevant in case of tmc-etr device.
- interrupts : <a b c> where a is 0 or 1 depending on if the interrupt is
spi/ppi, b is the interrupt number and c is the mask,
- interrupt-names : a list of strings that map in order to the list of
interrupts specified in the 'interrupts' property.
- qcom,sg-enable : indicates whether scatter gather feature is supported for TMC
ETR configuration.
- qcom,force-reg-dump : boolean, indicate whether TMC register need to be dumped.
Used for TMC component
- qcom,nidntsw : boolean, indicating NIDnT software debug or trace support
present. Used for tpiu component
- qcom,nidnthw : boolean, indicating NIDnT hardware sensing support present.
Used for tpiu component
qcom,nidntsw and qcom,nidnthw are mutually exclusive properties, either of
these may specified for tpiu component
- qcom,nidnt-swduart : boolean, indicating NIDnT swd uart support present. Used
for tpiu component
- qcom,nidnt-swdtrc : boolean, indicating NIDnT swd trace support present. Used
for tpiu component
- qcom,nidnt-jtag : boolean, indicating NIDnT jtag debug support present. Used
for tpiu component
- qcom,nidnt-spmi : boolean, indicating NIDnT spmi debug support present. Used
for tpiu component
- nidnt-gpio : specifies gpio for NIDnT hardware detection
- nidnt-gpio-polarity : specifies gpio polarity for NIDnT hardware detection
- pinctrl-names : names corresponding to the numbered pinctrl. The allowed
names are subset of the following: cti-trigin-pctrl,
cti-trigout-pctrl. Used for cti component
- pinctrl-<n>: list of pinctrl phandles for the different pinctrl states. Refer
to "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt".
- qcom,funnel-save-restore : boolean, indicating funnel port needs to be disabled
for the ETM whose CPU is being powered down. The port
state is restored when CPU is powered up. Used for
funnel component.
- qcom,tmc-flush-powerdown : boolean, indicating trace data needs to be flushed before
powering down CPU. Used for TMC component.
- qcom,bc-elem-size : specifies the BC element size supported by each monitor
connected to the aggregator on each port. Should be specified
in pairs (port, bc element size).
- qcom,tc-elem-size : specifies the TC element size supported by each monitor
connected to the aggregator on each port. Should be specified
in pairs (port, tc element size).
- qcom,dsb-elem-size : specifies the DSB element size supported by each monitor
connected to the aggregator on each port. Should be specified
in pairs (port, dsb element size).
- qcom,cmb-elem-size : specifies the CMB element size supported by each monitor
connected to the aggregator on each port. Should be specified
in pairs (port, cmb element size).
- qcom,clk-enable: specifies whether additional clock bit needs to be set for
M4M TPDM.
- qcom,tpda-atid : specifies the ATID for TPDA.
- qcom,inst-id : QMI instance id for remote ETMs.
- qcom,noovrflw-enable : boolean, indicating whether no overflow bit needs to be
set in ETM stall control register.
- coresight-cti-cpu : cpu phandle for cpu cti, required when qcom,cti-save is true
- coresight-etm-cpu : specifies phandle for the cpu associated with the ETM device
- qcom,dbgui-addr-offset : indicates the offset of dbgui address registers
- qcom,dbgui-data-offset : indicates the offset of dbgui data registers
- qcom,dbgui-size : indicates the size of dbgui address and data registers
- qcom,pmic-carddetect-gpio : indicates the hotplug capabilities of the qpdi driver
- qcom,cpuss-debug-cgc: debug clock gating phandle for etm
reg : the clock gating register for each cluster
cluster : indicate the cluster number
coresight-outports, coresight-child-list and coresight-child-ports lists will
be of the same length and will have a one to one correspondence among the
elements at the same list index.
coresight-default-sink must be specified for one of the sink devices that is
intended to be made the default sink. Other sink devices must not have this
specified. Not specifying this property on any of the sinks is invalid.
Examples:
1. Sinks
tmc_etr: tmc@fc322000 {
compatible = "arm,coresight-tmc";
reg = <0xfc322000 0x1000>,
<0xfc37c000 0x3000>;
reg-names = "tmc-base", "bam-base";
interrupts = <0 166 0>;
interrupt-names = "byte-cntr-irq";
qcom,byte-cntr-absent;
qcom,memory-size = <0x100000>;
coresight-id = <0>;
coresight-name = "coresight-tmc-etr";
coresight-nr-inports = <1>;
coresight-default-sink;
};
tpiu: tpiu@fc318000 {
compatible = "arm,coresight-tpiu";
reg = <0xfc318000 0x1000>;
reg-names = "tpiu-base";
coresight-id = <1>;
coresight-name = "coresight-tpiu";
coresight-nr-inports = <1>;
qcom,nidnt;
qcom,nidnthw;
nidnt-gpio = <38>;
nidnt-gpio-polarity = <1>;
vdd-supply = <&pm8941_l21>;
qcom,vdd-voltage-level = <2950000 2950000>;
qcom,vdd-current-level = <9000 800000>;
};
2. Links
funnel_merg: funnel@fc31b000 {
compatible = "arm,coresight-funnel";
reg = <0xfc31b000 0x1000>;
reg-names = "funnel-base";
coresight-id = <4>;
coresight-name = "coresight-funnel-merg";
coresight-nr-inports = <2>;
coresight-outports = <0>;
coresight-child-list = <&tmc_etf>;
coresight-child-ports = <0>;
};
funnel_in0: funnel@fc319000 {
compatible = "arm,coresight-funnel";
reg = <0xfc319000 0x1000>;
reg-names = "funnel-base";
coresight-id = <5>;
coresight-name = "coresight-funnel-in0";
coresight-nr-inports = <8>;
coresight-outports = <0>;
coresight-child-list = <&funnel_merg>;
coresight-child-ports = <0>;
};
tpda_lmh: tpda@fbb91000 {
compatible = "qcom,coresight-tpda";
reg = <0xfbb91000x1000>;
reg-names = "tpda-base";
coresight-id = <7>;
coresight-name = "coresight-tpda-lmh";
coresight-nr-inports = <32>;
coresight-outports = <0>;
coresight-child-list = <&funnel_in0>;
coresight-child-ports = <4>;
qcom,cmb-elem-size = <0 64>;
clocks = <&clock_rpm clk_qdss_clk>,
<&clock_rpm clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
3. Sources
tpdm_lmh: tpdm@fbb90000 {
compatible = "qcom,coresight-tpdm";
reg = <0xfbb90000x1000>;
reg-names = "tpdm-base";
coresight-id = <8>;
coresight-name = "coresight-tpdm-lmh";
coresight-nr-inports = <0>;
coresight-outports = <0>;
coresight-child-list = <&tpda_lmh>;
coresight-child-ports = <0>;
clocks = <&clock_rpm clk_qdss_clk>,
<&clock_rpm clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
dbgui: dbgui@86d000 {
compatible = "qcom,coresight-dbgui";
reg = <0x86d000 0x1000>;
reg-names = "dbgui-base";
coresight-id = <11>;
coresight-name = "coresight-dbgui";
coresight-nr-inports = <0>;
coresight-outports = <0>;
coresight-child-list = <&funnel_in3>;
coresight-child-ports = <2>;
qcom,dbgui-addr-offset = <0x30>;
qcom,dbgui-data-offset = <0xB0>;
qcom,dbgui-size = <32>;
clocks = <&clock_rpm clk_qdss_clk>,
<&clock_rpm clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
stm: stm@fc321000 {
compatible = "arm,coresight-stm";
reg = <0xfc321000 0x1000>,
<0xfa280000 0x180000>;
reg-names = "stm-base", "stm-data-base";
coresight-id = <9>;
coresight-name = "coresight-stm";
coresight-nr-inports = <0>;
coresight-outports = <0>;
coresight-child-list = <&funnel_in1>;
coresight-child-ports = <7>;
};
etm0: etm@fc33c000 {
compatible = "arm,coresight-etm";
reg = <0xfc33c000 0x1000>;
reg-names = "etm-base";
coresight-id = <10>;
coresight-name = "coresight-etm0";
coresight-nr-inports = <0>;
coresight-outports = <0>;
coresight-child-list = <&funnel_kpss>;
coresight-child-ports = <0>;
coresight-etm-cpu = <&CPU0>;
qcom,cpuss-debug-cgc = <&CGC_0>;
qcom,pc-save;
qcom,round-robin;
#address-cells = <1>;
#size-cells = <1>;
CGC_0: cluster-cgc {
reg = <0xb011088 0x4>;
cluster = <1>;
};
};
4. Miscellaneous
cti0: cti@fc308000 {
compatible = "arm,coresight-cti";
reg = <0xfc308000 0x1000>;
reg-names = "cti-base";
coresight-id = <15>;
coresight-name = "coresight-cti0";
coresight-nr-inports = <0>;
qcom,cti-gpio-trigout = <1>;
pinctrl-names = "cti-trigout-pctrl";
pinctrl-0 = <&trigout_a>;
};
cti1: cti@fc309000 {
compatible = "arm,coresight-cti";
reg = <0xfc309000 0x1000>;
reg-names = "cti-base";
coresight-id = <16>;
coresight-name = "coresight-cti1";
coresight-nr-inports = <0>;
};
hwevent: hwevent@fdf30018 {
compatible = "qcom,coresight-hwevent";
reg = <0xfdf30018 0x80>,
<0xf9011080 0x80>,
<0xfd4ab160 0x80>,
<0xfc401600 0x80>;
reg-names = "mmss-mux", "apcs-mux", "ppss-mux", "gcc-mux";
coresight-id = <29>;
coresight-name = "coresight-hwevent";
coresight-nr-inports = <0>;
qcom,hwevent-clks = "core_mmss_clk";
qcom,hwevent-regs = "gdsc_ufs";
};
fuse: fuse@fc4be024 {
compatible = "arm,coresight-fuse";
reg = <0xfc4be024 0x8>
<0x58040 0x4>;
reg-names = "fuse-base", "nidnt-fuse-base";
coresight-id = <30>;
coresight-name = "coresight-fuse";
coresight-nr-inports = <0>;
};

93
Documentation/devicetree/bindings/gpio/gpio-smp2p.txt Normal file
View File

@ -0,0 +1,93 @@
Qualcomm Technologies, Inc. SMSM Point-to-Point (SMP2P) GPIO Driver
Used to map an SMP2P entry and remote processor ID to a virtual GPIO controller
and virtual interrupt controller.
Required properties:
-compatible : should be "qcom,smp2pgpio";
-qcom,entry-name : name of the SMP2P entry
-qcom,remote-pid : the SMP2P remote processor ID (see smp2p_private_api.h)
-gpio-controller : specifies that this is a GPIO controller
-#gpio-cells : number of GPIO cells (should always be <2>)
-interrupt-controller : specifies that this is an interrupt controller
-#interrupt-cells : number of interrupt cells (should always be <2>)
Optional properties:
-qcom,is-inbound : specifies that this is an inbound entry (default is outbound)
Comments:
All device tree entries must be unique. Therefore to prevent naming collisions
between clients, it is recommended that the DT nodes should be named using the
format:
smp2pgpio_<ENTRY_NAME>_<REMOTE PID>_<in|out>
Unit test devices ("smp2p" entries):
-compatible : should be one of
"qcom,smp2pgpio_test_smp2p_1_out"
"qcom,smp2pgpio_test_smp2p_1_in"
"qcom,smp2pgpio_test_smp2p_2_out"
"qcom,smp2pgpio_test_smp2p_2_in"
"qcom,smp2pgpio_test_smp2p_3_out"
"qcom,smp2pgpio_test_smp2p_3_in"
"qcom,smp2pgpio_test_smp2p_4_out"
"qcom,smp2pgpio_test_smp2p_4_in"
"qcom,smp2pgpio_test_smp2p_7_out"
"qcom,smp2pgpio_test_smp2p_7_in"
"qcom,smp2pgpio_test_smp2p_15_out"
"qcom,smp2pgpio_test_smp2p_15_in"
-gpios : the relevant gpio pins of the entry
Example:
/* Maps inbound "smp2p" entry on remote PID 7 to GPIO controller. */
smp2pgpio_smp2p_7_in: qcom,smp2pgpio-smp2p-7-in {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <7>;
qcom,is-inbound;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/*
* Maps inbound "smp2p" entry on remote PID 7 to client driver
* "qcom,smp2pgpio_test_smp2p_7_in".
*
* Note: If all 32-pins are used by this client, then you
* can just list pin 0 here as a shortcut.
*/
qcom,smp2pgpio_test_smp2p_7_in {
compatible = "qcom,smp2pgpio_test_smp2p_7_in";
gpios = <&smp2pgpio_smp2p_7_in 0 0>, /* pin 0 */
<&smp2pgpio_smp2p_7_in 1 0>,
. . .
<&smp2pgpio_smp2p_7_in 31 0>; /* pin 31 */
};
/* Maps outbound "smp2p" entry on remote PID 7 to GPIO controller. */
smp2pgpio_smp2p_7_out: qcom,smp2pgpio-smp2p-7-out {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <7>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/*
* Maps outbound "smp2p" entry on remote PID 7 to client driver
* "qcom,smp2pgpio_test_smp2p_7_out".
*
* Note: If all 32-pins are used by this client, then you
* can just list pin 0 here as a shortcut.
*/
qcom,smp2pgpio_test_smp2p_7_out {
compatible = "qcom,smp2pgpio_test_smp2p_7_out";
gpios = <&smp2pgpio_smp2p_7_out 0 0>, /* pin 0 */
<&smp2pgpio_smp2p_7_out 1 0>,
. . .
<&smp2pgpio_smp2p_7_out 31 0>; /* pin 31 */
};

224
Documentation/devicetree/bindings/gpio/qpnp-pin.txt Normal file
View File

@ -0,0 +1,224 @@
* msm-qpnp-pin
msm-qpnp-pin is a GPIO chip driver for the MSM SPMI implementation.
It creates a spmi_device for every spmi-dev-container block of device_nodes.
These device_nodes contained within specify the PMIC pin number associated
with each gpio chip. The driver will map these to Linux GPIO numbers.
[PMIC GPIO Device Declarations]
-Root Node-
Required properties :
- spmi-dev-container : Used to specify the following child nodes as part of the
same SPMI device.
- gpio-controller : Specify as gpio-controller. All child nodes will belong to
this gpio_chip.
- #gpio-cells: We encode a PMIC pin number and a 32-bit flag field to
specify the gpio configuration. This must be set to '2'.
- #address-cells: Specify one address field. This must be set to '1'.
- #size-cells: Specify one size-cell. This must be set to '1'.
- compatible = "qcom,qpnp-pin" : Specify driver matching for this driver.
- label: String giving the name for the gpio_chip device. This name
should be unique on the system and portray the specifics of the device.
-Child Nodes-
Required properties :
- reg : Specify the spmi offset and size for this pin device.
- qcom,pin-num : Specify the PMIC pin number for this device.
Optional configuration properties :
- qcom,mode: indicates whether the pin should be input, output, or
both for gpios. mpp pins also support bidirectional,
analog in, analog out and current sink.
QPNP_PIN_MODE_DIG_IN = 0, (GPIO/MPP)
QPNP_PIN_MODE_DIG_OUT = 1, (GPIO/MPP)
QPNP_PIN_MODE_DIG_IN_OUT = 2, (GPIO/MPP)
QPNP_PIN_MODE_ANA_PASS_THRU = 3, (GPIO_LV/GPIO_MV)
QPNP_PIN_MODE_BIDIR = 3, (MPP)
QPNP_PIN_MODE_AIN = 4, (MPP)
QPNP_PIN_MODE_AOUT = 5, (MPP)
QPNP_PIN_MODE_SINK = 6 (MPP)
- qcom,output-type: indicates gpio should be configured as CMOS or open
drain.
QPNP_PIN_OUT_BUF_CMOS = 0, (GPIO)
QPNP_PIN_OUT_BUF_OPEN_DRAIN_NMOS = 1, (GPIO)
QPNP_PIN_OUT_BUF_OPEN_DRAIN_PMOS = 2 (GPIO)
QPNP_PIN_OUT_BUF_NO_DRIVE = 3, (GPIO_LV/GPIO_MV)
- qcom,invert: Invert the signal of the gpio line -
QPNP_PIN_INVERT_DISABLE = 0 (GPIO/MPP)
QPNP_PIN_INVERT_ENABLE = 1 (GPIO/MPP)
- qcom,pull: This parameter should be programmed to different values
depending on whether it's GPIO or MPP.
For GPIO, it indicates whether a pull up or pull down
should be applied. If a pullup is required the
current strength needs to be specified.
Current values of 30uA, 1.5uA, 31.5uA, 1.5uA with 30uA
boost are supported. This value should be one of
the QPNP_PIN_GPIO_PULL_*. Note that the hardware ignores
this configuration if the GPIO is not set to input or
output open-drain mode.
QPNP_PIN_PULL_UP_30 = 0, (GPIO)
QPNP_PIN_PULL_UP_1P5 = 1, (GPIO)
QPNP_PIN_PULL_UP_31P5 = 2, (GPIO)
QPNP_PIN_PULL_UP_1P5_30 = 3, (GPIO)
QPNP_PIN_PULL_DN = 4, (GPIO)
QPNP_PIN_PULL_NO = 5 (GPIO)
For MPP, it indicates whether a pullup should be
applied for bidirectitional mode only. The hardware
ignores the configuration when operating in other modes.
This value should be one of the QPNP_PIN_MPP_PULL_*.
QPNP_PIN_MPP_PULL_UP_0P6KOHM = 0, (MPP)
QPNP_PIN_MPP_PULL_UP_OPEN = 1 (MPP)
QPNP_PIN_MPP_PULL_UP_10KOHM = 2, (MPP)
QPNP_PIN_MPP_PULL_UP_30KOHM = 3, (MPP)
- qcom,vin-sel: specifies the voltage level when the output is set to 1.
For an input gpio specifies the voltage level at which
the input is interpreted as a logical 1.
QPNP_PIN_VIN0 = 0, (GPIO/MPP/GPIO_LV/GPIO_MV)
QPNP_PIN_VIN1 = 1, (GPIO/MPP/GPIO_MV)
QPNP_PIN_VIN2 = 2, (GPIO/MPP)
QPNP_PIN_VIN3 = 3, (GPIO/MPP)
QPNP_PIN_VIN4 = 4, (GPIO/MPP)
QPNP_PIN_VIN5 = 5, (GPIO/MPP)
QPNP_PIN_VIN6 = 6, (GPIO/MPP)
QPNP_PIN_VIN7 = 7 (GPIO/MPP)
- qcom,out-strength: the amount of current supplied for an output gpio.
QPNP_PIN_OUT_STRENGTH_LOW = 1 (GPIO)
QPNP_PIN_OUT_STRENGTH_MED = 2, (GPIO)
QPNP_PIN_OUT_STRENGTH_HIGH = 3, (GPIO)
- qcom,dtest-sel Route the pin internally to a DTEST line.
QPNP_PIN_DIG_IN_CTL_DTEST1 = 1 (GPIO/MPP)
QPNP_PIN_DIG_IN_CTL_DTEST2 = 2, (GPIO/MPP)
QPNP_PIN_DIG_IN_CTL_DTEST3 = 3, (GPIO/MPP)
QPNP_PIN_DIG_IN_CTL_DTEST4 = 4, (GPIO/MPP)
- qcom,src-sel: select a function for the pin. Certain pins
can be paired (shorted) with each other. Some gpio pins
can act as alternate functions.
In the context of gpio, this acts as a source select.
For mpps, this is an enable select.
QPNP_PIN_SEL_FUNC_CONSTANT = 0, (GPIO/MPP)
QPNP_PIN_SEL_FUNC_PAIRED = 1, (GPIO/MPP)
QPNP_PIN_SEL_FUNC_1 = 2, (GPIO/MPP)
QPNP_PIN_SEL_FUNC_2 = 3, (GPIO/MPP)
QPNP_PIN_SEL_DTEST1 = 4, (GPIO/MPP)
QPNP_PIN_SEL_DTEST2 = 5, (GPIO/MPP)
QPNP_PIN_SEL_DTEST3 = 6, (GPIO/MPP)
QPNP_PIN_SEL_DTEST4 = 7 (GPIO/MPP)
Below are the source-select values for GPIO_LV/MV.
QPNP_PIN_LV_MV_SEL_FUNC_CONSTANT = 0, (GPIO_LV/GPIO_MV)
QPNP_PIN_LV_MV_SEL_FUNC_PAIRED = 1, (GPIO_LV/GPIO_MV)
QPNP_PIN_LV_MV_SEL_FUNC_1 = 2, (GPIO_LV/GPIO_MV)
QPNP_PIN_LV_MV_SEL_FUNC_2 = 3, (GPIO_LV/GPIO_MV)
QPNP_PIN_LV_MV_SEL_FUNC_3 = 4, (GPIO_LV/GPIO_MV)
QPNP_PIN_LV_MV_SEL_FUNC_4 = 5, (GPIO_LV/GPIO_MV)
QPNP_PIN_LV_MV_SEL_DTEST1 = 6 (GPIO_LV/GPIO_MV)
QPNP_PIN_LV_MV_SEL_DTEST2 = 7, (GPIO_LV/GPIO_MV)
QPNP_PIN_LV_MV_SEL_DTEST3 = 8, (GPIO_LV/GPIO_MV)
QPNP_PIN_LV_MV_SEL_DTEST4 = 9, (GPIO_LV/GPIO_MV)
- qcom,master-en: 1 = Enable features within the
pin block based on configurations. (GPIO/MPP)
0 = Completely disable the block and
let the pin float with high impedance
regardless of other settings. (GPIO/MPP)
- qcom,aout-ref: set the analog output reference.
QPNP_PIN_AOUT_1V25 = 0, (MPP)
QPNP_PIN_AOUT_0V625 = 1, (MPP)
QPNP_PIN_AOUT_0V3125 = 2, (MPP)
QPNP_PIN_AOUT_MPP = 3, (MPP)
QPNP_PIN_AOUT_ABUS1 = 4, (MPP)
QPNP_PIN_AOUT_ABUS2 = 5, (MPP)
QPNP_PIN_AOUT_ABUS3 = 6, (MPP)
QPNP_PIN_AOUT_ABUS4 = 7 (MPP)
- qcom,ain-route: Set the destination for analog input.
QPNP_PIN_AIN_AMUX_CH5 = 0, (MPP)
QPNP_PIN_AIN_AMUX_CH6 = 1, (MPP)
QPNP_PIN_AIN_AMUX_CH7 = 2, (MPP)
QPNP_PIN_AIN_AMUX_CH8 = 3, (MPP)
QPNP_PIN_AIN_AMUX_ABUS1 = 4, (MPP)
QPNP_PIN_AIN_AMUX_ABUS2 = 5, (MPP)
QPNP_PIN_AIN_AMUX_ABUS3 = 6, (MPP)
QPNP_PIN_AIN_AMUX_ABUS4 = 7 (MPP)
- qcom,cs-out: Set the the amount of output to sync in mA.
QPNP_PIN_CS_OUT_5MA = 0, (MPP)
QPNP_PIN_CS_OUT_10MA = 1, (MPP)
QPNP_PIN_CS_OUT_15MA = 2, (MPP)
QPNP_PIN_CS_OUT_20MA = 3, (MPP)
QPNP_PIN_CS_OUT_25MA = 4, (MPP)
QPNP_PIN_CS_OUT_30MA = 5, (MPP)
QPNP_PIN_CS_OUT_35MA = 6, (MPP)
QPNP_PIN_CS_OUT_40MA = 7 (MPP)
- qcom,apass-sel: Set the ATEST channel to route the signal
QPNP_PIN_APASS_SEL_ATEST1 = 0, (GPIO_LV/GPIO_MV)
QPNP_PIN_APASS_SEL_ATEST2 = 1, (GPIO_LV/GPIO_MV)
QPNP_PIN_APASS_SEL_ATEST3 = 2, (GPIO_LV/GPIO_MV)
QPNP_PIN_APASS_SEL_ATEST4 = 3, (GPIO_LV/GPIO_MV)
*Note: If any of the configuration properties are not specified, then the
qpnp-pin driver will not modify that respective configuration in
hardware.
[PMIC GPIO clients]
Required properties :
- gpios : Contains 3 fields of the form <&gpio_controller pmic_pin_num flags>
[Example]
qpnp: qcom,spmi@fc4c0000 {
#address-cells = <1>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <3>;
qcom,pm8941@0 {
spmi-slave-container;
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
pm8941_gpios: gpios {
spmi-dev-container;
compatible = "qcom,qpnp-pin";
gpio-controller;
#gpio-cells = <2>;
#address-cells = <1>;
#size-cells = <1>;
gpio@c000 {
reg = <0xc000 0x100>;
qcom,pin-num = <62>;
};
gpio@c100 {
reg = <0xc100 0x100>;
qcom,pin-num = <20>;
qcom,source_sel = <2>;
qcom,pull = <5>;
};
};
qcom,testgpio@1000 {
compatible = "qcom,qpnp-testgpio";
reg = <0x1000 0x1000>;
gpios = <&pm8941_gpios 62 0x0 &pm8941_gpios 20 0x1>;
};
};
};
};

197
Documentation/devicetree/bindings/hwmon/qpnp-adc-voltage.txt Normal file
View File

@ -0,0 +1,197 @@
Qualcomm Technologies, Inc. QPNP PMIC Voltage ADC Arbiter
QPNP PMIC Voltage ADC (VADC) provides interface to clients to read
Voltage. A 15 bit ADC is used for Voltage measurements. There are multiple
peripherals to the VADC and the scope of the driver is to provide interface
for the USR peripheral of the VADC.
VADC node
Required properties:
- compatible : should be "qcom,qpnp-vadc" for Voltage ADC device driver and
"qcom,qpnp-vadc-hc" for VADC_HC voltage ADC device driver.
- reg : offset and length of the PMIC Aribter register map.
- address-cells : Must be one.
- size-cells : Must be zero.
- interrupts : The USR bank peripheral VADC interrupt.
- interrupt-names : Should contain "eoc-int-en-set" for EOC,
"high-thr-en-set" for high threshold interrupts and
"low-thr-en-set" for low threshold interrupts. High and low threshold
interrupts are to be enabled if VADC_USR needs to support recurring measurement.
- qcom,adc-bit-resolution : Bit resolution of the ADC.
- qcom,adc-vdd-reference : Voltage reference used by the ADC.
Channel nodes
NOTE: Atleast one Channel node is required.
Optional properties:
- qcom,vadc-poll-eoc: Use polling instead of interrupts for End of Conversion completion.
- qcom,pmic-revid : Phandle pointing to the revision peripheral node. Use it to query the
PMIC type and revision for applying the appropriate temperature
compensation parameters.
-qcom,vadc-meas-int-mode : Enable VADC_USR to handle requests to perform recurring measurements
for any one supported channel along with supporting single conversion
requests.
- qcom,vadc-recalib-check: Add this property to check if recalibration required due to inaccuracy.
- qcom,vadc-thermal-node : If present a thermal node is created and the channel is registered as
part of the thermal sysfs which allows clients to use the thermal framework
to set temperature thresholds and receive notification when the temperature
crosses a set threshold, read temperature and enable/set trip types supported
by the thermal framework.
- hkadc_ldo-supply : Add this property if VADC needs to perform a Software Vote for the HKADC.
- hkadc_ok-supply : Add this property if the VADC needs to perform a Software vote for the HKADC VREG_OK.
- qcom,cal-val : Add this property for VADC_HC voltage ADC device to select from the following
unsigned int. If the property is not present the default calibration value of
using the timer value is chosen.
0 : The calibration values used for measurement are from a timer.
1 : Forces a fresh measurement for calibration values at the same time
measurement is taken.
Client required property:
- qcom,<consumer name>-vadc : The phandle to the corresponding vadc device.
The consumer name passed to the driver when calling
qpnp_get_vadc() is used to associate the client
with the corresponding device.
Required properties:
- label : Channel name used for sysfs entry.
- reg : AMUX channel number.
- qcom,decimation : Sampling rate to use for the individual channel measurement.
Select from following unsigned int for Voltage ADC device.
0 : 512
1 : 1K
2 : 2K
3 : 4K
Select from following unsigned int for VADC_HC voltage ADC device.
0 : 256
1 : 512
2 : 1024
- qcom,pre-div-channel-scaling : Pre-div used for the channel before the signal
is being measured. Some of the AMUX channels
support dividing the signal from a predetermined
ratio. The configuration for this node is to know
the pre-determined ratio and use it for post scaling.
Select from the following unsigned int.
0 : {1, 1}
1 : {1, 3}
2 : {1, 4}
3 : {1, 6}
4 : {1, 20}
5 : {1, 8}
6 : {10, 81}
7 : {1, 10}
- qcom,calibration-type : Reference voltage to use for channel calibration.
Channel calibration is dependendent on the channel.
Certain channels like XO_THERM, BATT_THERM use ratiometric
calibration. Most other channels fall under absolute calibration.
Select from the following strings.
"absolute" : Uses the 625mv and 1.25V reference channels.
"ratiometric" : Uses the reference Voltage/GND for calibration.
- qcom,scale-function : Scaling function used to convert raw ADC code to units specific to
a given channel.
Select from the following unsigned int.
0 : Default scaling to convert raw adc code to voltage.
1 : Conversion to temperature based on btm parameters.
2 : Returns result in degC for 100k pull-up.
3 : Returns current across 0.1 ohm resistor.
4 : Returns XO thermistor voltage in degree's Centigrade.
5 : Returns result in degC for 150k pull-up.
9 : Conversion to temperature based on -15~55 allowable
battery charging tempeature setting for btm parameters.
- qcom,hw-settle-time : Settling period for the channel before ADC read.
Select from the following unsigned int.
0 : 0us
1 : 100us
2 : 200us
3 : 300us
4 : 400us
5 : 500us
6 : 600us
7 : 700us
8 : 800us
9 : 900us
0xa : 1ms
0xb : 2ms
0xc : 4ms
0xd : 6ms
0xe : 8ms
0xf : 10ms
- qcom,fast-avg-setup : Average number of samples to be used for measurement. Fast averaging
provides the option to obtain a single measurement from the ADC that
is an average of multiple samples. The value selected is 2^(value)
Select from the following unsigned int for Voltage ADC device.
0 : 1
1 : 2
2 : 4
3 : 8
4 : 16
5 : 32
6 : 64
7 : 128
8 : 256
Select from the following unsigned int for VADC_HC ADC device.
0 : 1
1 : 2
2 : 4
3 : 8
4 : 16
Example:
/* Main Node */
qcom,vadc@3100 {
compatible = "qcom,qpnp-vadc";
reg = <0x3100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x0 0x31 0x0>;
interrupt-names = "eoc-int-en-set";
qcom,adc-bit-resolution = <15>;
qcom,adc-vdd-reference = <1800>;
/* Channel Node */
chan@0 {
label = "usb_in";
reg = <0>;
qcom,decimation = <0>;
qcom,pre-div-channel-scaling = <4>;
qcom,calibration-type = "absolute";
qcom,scale-function = <0>;
qcom,hw-settle-time = <0>;
qcom,fast-avg-setup = <0>;
};
};
Client device example:
/* Add to the clients node that needs the VADC channel A/D */
client_node {
qcom,client-vadc = <&pm8941_vadc>;
};
/* Clients have an option of measuring an analog signal through an MPP.
MPP block is not part of the VADC block but is an individual PMIC
block that has an option to support clients to configure an MPP as
an analog input which can be routed through one of the VADC pre-mux
inputs. Here is an example of how to configure an MPP as an analog
input */
/* Configure MPP4 as an Analog input to AMUX8 and read from channel 0x23 */
/* MPP DT configuration in the platform DT file*/
mpp@a300 { /* MPP 4 */
qcom,mode = <4>; /* AIN input */
qcom,invert = <1>; /* Enable MPP */
qcom,ain-route = <3>; /* AMUX 8 */
qcom,master-en = <1>;
qcom,src-sel = <0>; /* Function constant */
};
/* VADC Channel configuration */
chan@23 {
label = "mpp4_div3";
reg = <0x23>;
qcom,decimation = <0>;
qcom,pre-div-channel-scaling = <1>;
qcom,calibration-type = "absolute";
qcom,scale-function = <0>;
qcom,hw-settle-time = <0>;
qcom,fast-avg-setup = <0>;
};

27
Documentation/devicetree/bindings/net/can/k61-can.txt Normal file
View File

@ -0,0 +1,27 @@
* Kinetis K61 CAN *
This driver implements SPI slave protocol for Freescale K61 CAN controller.
Required properties:
- compatible: Should be "fsl,k61".
- reg: Should contain SPI chip select.
- interrupt-parent: Should specify interrupt controller for the interrupt.
- interrupts: Should contain IRQ line for the CAN controller.
- reset-gpio: Reference to the GPIO connected to the reset input.
- pinctrl-names : Names corresponding to the numbered pinctrl states.
- pinctrl-0 : This explains the active state of the GPIO line.
- pinctrl-1 : This explains the suspend state of the GPIO line.
Example:
can-controller@0 {
compatible = "fsl,k61";
reg = <0>;
interrupt-parent = <&tlmm_pinmux>;
interrupts = <25 0>;
reset-gpio = <&tlmm_pinmux 11 0x1>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&can_rst_on>;
pinctrl-1 = <&can_rst_off>;
};

197
Documentation/devicetree/bindings/net/msm-emac.txt Normal file
View File

@ -0,0 +1,197 @@
Qualcomm Technologies, Inc. EMAC Gigabit Ethernet Controller
This network controller consists of two devices: a MAC and an
internal PHY (SGMII/RGMII). Each device is represented by a device tree node.
A phandle connects the MAC node to its corresponding internal phy node.
Another phandle points to the external PHY node.
Required properties:
MAC node:
- compatible : Should be "qcom,mdm9607-emac" for mdm9607 based EMAC driver
Should be "qcom,emac" for other targets based EMAC driver
- reg : Offset and length of the register regions for the device
- reg-names : Register region names referenced in 'reg' above.
Required register resource entries are:
"emac" : EMAC controller register block.
"emac_csr" : EMAC wrapper register block.
Optional register resource entries are:
"emac_1588" : EMAC 1588 (PTP) register block.
Required if 'qcom,emac-tstamp-en' is present.
- interrupts : Interrupt number used by this controller
- interrupt-names : Interrupt resource names referenced in 'interrupts' above.
Required interrupt resource entries are:
"emac_core0_irq" : EMAC core0 interrupt.
"emac_core1_irq" : EMAC core1 interrupt.
"emac_core2_irq" : EMAC core2 interrupt.
"emac_core3_irq" : EMAC core3 interrupt.
Optional interrupt resource entries are:
"emac_wol_irq" : EMAC Wake-On-LAN (WOL) interrupt.
Required if WOL is supported.
- phy-mode: String, operation mode of the PHY interface. See ethernet.txt in the
same directory.
- internal-phy : phandle to the internal PHY node
- phy-handle : phandle the the external PHY node
Internal PHY node:
- compatible : Should be "qcom,mdm9607-emac-sgmii" for mdm9607.
Should be "qcom,qdf2432-emac-sgmii" for QDF2432
Should be "qcom,fsm9900-emac-sgmii" for FSM9900
- reg : Offset and length of the register region(s) for the device
- reg-names : Register region names referenced in 'reg' above.
"emac_sgmii" : EMAC SGMII PHY register block.
Required if 'phy-mode' is "sgmii".
- interrupts : Interrupt number used by this controller
- interrupt-names : Interrupt resource names referenced in 'interrupts' above.
"emac_sgmii_irq" : EMAC SGMII interrupt.
Required if 'phy-mode' is "sgmii".
The external phy child node:
- reg : The phy address
Optional properties:
MAC node:
- qcom,emac-tstamp-en : Enables the PTP (1588) timestamping feature.
Include this only if PTP (1588) timestamping
feature is needed. If included, "emac_1588" register
base should be specified.
- mac-address : The 6-byte MAC address. If present, it is the default
MAC address.
- qcom,no-external-phy : Indicates there is no external PHY connected to EMAC.
Include this only if the EMAC is directly connected to
the peer end without EPHY.
- qcom,emac-ptp-grandmaster : Enable the PTP (1588) grandmaster mode.
Include this only if PTP (1588) is configured as
grandmaster.
- qcom,emac-ptp-frac-ns-adj : The vector table to adjust the fractional ns per
RTC clock cycle.
Include this only if there is accuracy loss of
fractional ns per RTC clock cycle. For individual
table entry, the first field indicates the RTC
reference clock rate. The second field indicates
the number of adjustment in 2 ^ -26 ns.
- tstamp-eble : Enables the PTP (1588) timestamping feature in ACPI mode.
- <supply-name>-supply: phandle to the regulator device tree node
Required "supply-name" are "emac_vreg*"
- qcom,vdd-voltage-level: This property must be a list of five integer
values (max voltage value for supply 1/2/3/4/5) where each value
represents a voltage in microvolts.
Example:
FSM9900:
soc {
#address-cells = <1>;
#size-cells = <1>;
emac0: ethernet@feb20000 {
compatible = "qcom,fsm9900-emac";
reg-names = "emac", "emac_csr", "emac_1588";
reg = <0xfeb20000 0x10000>,
<0xfeb36000 0x1000>,
<0xfeb3c000 0x4000>,
interrupts = <0 76 0>, <0 77 0>, <0 78 0>, <0 79 0>;
interrupt-names = "emac_core0_irq", "emac_core1_irq",
"emac_core2_irq", "emac_core3_irq";
clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>,
<&gcc 6>, <&gcc 7>;
clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk",
"mdio_clk", "tx_clk", "rx_clk", "sys_clk";
internal-phy = <&emac_sgmii>;
phy-handle = <&phy0>;
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins_a>;
};
emac_sgmii: ethernet@feb38000 {
compatible = "qcom,fsm9900-emac-sgmii";
reg-names = "emac_sgmii";
reg = <0xfeb38000 0x1000>;
interrupts = <80>;
};
tlmm: pinctrl@fd510000 {
compatible = "qcom,fsm9900-pinctrl";
mdio_pins_a: mdio {
state {
pins = "gpio123", "gpio124";
function = "mdio";
};
};
};
MDM9607:
emac0: qcom,emac@7c40000 {
compatible = "qcom,mdm9607-emac";
reg-names = "emac", "emac_csr", "emac_1588";
reg = <0x7c40000 0x10000>,
<0x7c56000 0x1000>,
<0x7c5c000 0x4000>;
#address-cells = <0>;
interrupt-parent = <&emac0>;
#interrupt-cells = <1>;
interrupts = <0 1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 76 0
1 &tlmm_pinmux 30 0x8>;
interrupt-names = "emac_core0_irq", "emac_wol_irq";
emac_vreg1-supply = <&mdm9607_l1>;
emac_vreg2-supply = <&mdm9607_l3>;
emac_vreg3-supply = <&mdm9607_l5>;
emac_vreg4-supply = <&mdm9607_l11>;
emac_vreg5-supply = <&emac_lan_vreg>;
qcom,vdd-voltage-level = <1250000 1800000 2850000 1800000 0>;
clocks = <&clock_gcc clk_gcc_emac_0_axi_clk>,
<&clock_gcc clk_gcc_emac_0_ahb_clk>,
<&clock_gcc clk_gcc_emac_0_125m_clk>,
<&clock_gcc clk_gcc_emac_0_sys_25m_clk>,
<&clock_gcc clk_gcc_emac_0_tx_clk>,
<&clock_gcc clk_gcc_emac_0_rx_clk>,
<&clock_gcc clk_gcc_emac_0_sys_clk>;
clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk",
"mdio_clk", "tx_clk", "rx_clk", "sys_clk";
internal-phy = <&emac_sgmii>;
phy-handle = <&phy0>;
phy-mode = "sgmii";
pinctrl-names = "emac_mdio_active", "emac_mdio_sleep",
"emac_ephy_active", "emac_ephy_sleep";
pinctrl-0 = <&emac0_mdio_active>;
pinctrl-1 = <&emac0_mdio_sleep>;
pinctrl-2 = <&emac0_ephy_active>;
pinctrl-3 = <&emac0_ephy_sleep>;
qcom,emac-tstamp-en;
qcom,emac-ptp-frac-ns-adj = <125000000 1>;
status = "disable";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
emac_sgmii: ethernet@7c58000 {
compatible = "qcom,mdm9607-emac-sgmii";
reg-names = "emac_sgmii";
reg = <0x7c58000 0x400>;
interrupt-names = "emac_sgmii_irq";
interrupts = <0 80 0>;
};

140
Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt Normal file
View File

@ -0,0 +1,140 @@
Qualcomm Technologies, Inc. MSS QDSP6v5 Peripheral Image Loader
pil-qdsp6v5-mss is a peripheral image loader (PIL) driver. It is used for
loading QDSP6v5 (Hexagon) firmware images for modem subsystems into memory and
preparing the subsystem's processor to execute code. It's also responsible for
shutting down the processor when it's not needed.
Required properties:
- compatible: Must be "qcom,pil-q6v5-mss" or "qcom,pil-q6v55-mss" or
"pil-q6v56-mss".
- reg: Pairs of physical base addresses and region sizes of
memory mapped registers.
- reg-names: Names of the bases for the above registers. "qdsp6_base",
"rmb_base", "restart_reg" or "restart_reg_sec"(optional
for secure mode) are expected.
If "halt_base" is in same 4K pages this register then
this will be defined else "halt_q6", "halt_modem",
"halt_nc" is required.
- interrupts: The modem watchdog interrupt
- vdd_cx-supply: Reference to the regulator that supplies the vdd_cx domain.
- vdd_cx-voltage: Voltage corner/level(max) for cx rail.
- vdd_mx-supply: Reference to the regulator that supplies the memory rail.
- vdd_mx-uV: Voltage setting for the mx rail.
- qcom,firmware-name: Base name of the firmware image. Ex. "mdsp"
Optional properties:
- vdd_mss-supply: Reference to the regulator that supplies the processor.
This may be a shared regulator that is already voted
on in the PIL proxy voting code (and also managed by the
modem on its own), hence we mark it as as optional.
- vdd_pll-supply: Reference to the regulator that supplies the PLL's rail.
- qcom,vdd_pll: Voltage to be set for the PLL's rail.
- reg-names: "cxrail_bhs_reg" - control register for modem power
domain.
- clocks: Array of <clock_controller_phandle clock_reference> listing
all the clocks that are accesed by this subsystem.
- qcom,proxy-clock-names: Names of the clocks that need to be turned on/off during
proxy voting/unvoting.
- qcom,active-clock-names: Names of the clocks that need to be turned on for the
subsystem to run. Turned off when the subsystem is shutdown.
- clock-names: Names of all the clocks that are accessed by the subsystem.
- qcom,is-not-loadable: Boolean- Present if the image does not need to
be loaded.
- qcom,pil-self-auth: Boolean- True if authentication is required.
- qcom,mem-protect-id: Virtual ID used by PIL to call into TZ/HYP to protect/unprotect
subsystem related memory.
- qcom,gpio-err-fatal: GPIO used by the modem to indicate error fatal to the apps.
- qcom,gpio-err-ready: GPIO used by the modem to indicate error ready to the apps.
- qcom,gpio-proxy-unvote: GPIO used by the modem to trigger proxy unvoting in
the apps.
- qcom,gpio-force-stop: GPIO used by the apps to force the modem to shutdown.
- qcom,gpio-stop-ack: GPIO used by the modem to ack force stop or a graceful stop
to the apps.
- qcom,gpio-ramdump-disable: GPIO used by the modem to inform the apps that ramdump
collection should be disabled.
- qcom,gpio-shutdown-ack: GPIO used by the modem to indicate that it has done the
necessary cleanup and that the apps can move forward with
the shutdown sequence.
- qcom,restart-group: List of subsystems that will need to restart together.
- qcom,mba-image-is-not-elf: Boolean- Present if MBA image doesn't use the ELF
format.
- qcom,ssctl-instance-id: Instance id used by the subsystem to connect with the SSCTL
service.
- qcom,sysmon-id: platform device id that sysmon is probed with for the subsystem.
- qcom,override-acc: Boolean- Present if we need to override the default ACC settings
- qcom,ahb-clk-vote: Boolean- Present if we need to remove the vote for the mss_cfg_ahb
clock after the modem boots up
- qcom,pnoc-clk-vote: Boolean- Present if the modem needs the PNOC bus to be
clocked before it boots up
- qcom,qdsp6v56-1-3: Boolean- Present if the qdsp version is v56 1.3
- qcom,qdsp6v56-1-5: Boolean- Present if the qdsp version is v56 1.5
- qcom,edge: GLINK logical name of the remote subsystem
- qcom,pil-force-shutdown: Boolean. If set, the SSR framework will not trigger graceful shutdown
on behalf of the subsystem driver.
- qcom,pil-mss-memsetup: Boolean - True if TZ need to be informed of modem start address and size.
- qcom,pas-id: pas_id of the subsystem.
- qcom,qdsp6v56-1-8: Boolean- Present if the qdsp version is v56 1.8
- qcom,qdsp6v56-1-8-inrush-current: Boolean- Present if the qdsp version is V56 1.8 and has in-rush
current issue.
- qcom,qdsp6v61-1-1: Boolean- Present if the qdsp version is v61 1.1
- qcom,qdsp6v62-1-2: Boolean- Present if the qdsp version is v62 1.2
- qcom,qdsp6v62-1-4: Boolean- Present if the qdsp version is v62 1.4
- qcom,qdsp6v62-1-5: Boolean- Present if the qdsp version is v62 1.5
- qcom,mx-spike-wa: Boolean- Present if we need to assert QDSP6 I/O clamp, memory
wordline clamp, and compiler memory clamp during MSS restart.
- qcom,qdsp6v56-1-10: Boolean- Present if the qdsp version is v56 1.10
- qcom,override-acc-1: Override the default ACC settings with this value if present.
One child node to represent the MBA image may be specified, when the MBA image
needs to be loaded in a specifically carved out memory region.
Required properties:
- compatible: Must be "qcom,pil-mba-mem"
- memory-region: A phandle that points to a reserved memory where the MBA image will be loaded.
Example:
qcom,mss@fc880000 {
compatible = "qcom,pil-q6v5-mss";
reg = <0xfc880000 0x100>,
<0xfd485000 0x400>,
<0xfc820000 0x020>,
<0xfc401680 0x004>;
reg-names = "qdsp6_base", "halt_base", "rmb_base",
"restart_reg";
interrupts = <0 24 1>;
vdd_mss-supply = <&pm8841_s3>;
vdd_cx-supply = <&pm8841_s2>;
vdd_cx-voltage = <7>;
vdd_mx-supply = <&pm8841_s1>;
vdd_mx-uV = <105000>;
clocks = <&clock_rpm clk_xo_pil_mss_clk>,
<&clock_gcc clk_gcc_mss_cfg_ahb_clk>,
<&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>,
<&clock_gcc clk_gcc_boot_rom_ahb_clk>;
clock-names = "xo", "iface_clk", "bus_clk", "mem_clk";
qcom,proxy-clock-names = "xo";
qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk";
qcom,is-not-loadable;
qcom,firmware-name = "mba";
qcom,pil-self-auth;
qcom,mba-image-is-not-elf;
qcom,override-acc;
/* GPIO inputs from mss */
qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
/* GPIO output to mss */
qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
qcom,ssctl-instance-id = <12>;
qcom,sysmon-id = <0>;
qcom,mba-mem@0 {
compatible = "qcom,pil-mba-mem";
memory-region = <&peripheral_mem>;
};
};

191
Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-pinctrl.txt Normal file
View File

@ -0,0 +1,191 @@
Qualcomm Technologies, Inc. MDM9607 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
MDM9607 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,mdm9607-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
- qcom,tlmm-emmc-boot-select:
Usage: optional
Value type: <u32>
Definition: selects the bit-field position to set.
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode. Valid pins are:
gpio0-gpio79,
sdc1_clk,
sdc1_cmd,
sdc1_data,
sdc2_clk,
sdc2_cmd,
sdc2_data,
qdsd_clk,
qdsd_cmd,
qdsd_data0,
qdsd_data1,
qdsd_data2,
qdsd_data3
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
blsp_spi3, blsp_uart3, qdss_tracedata_a, bimc_dte1, blsp_i2c3,
qdss_traceclk_a, bimc_dte0, qdss_cti_trig_in_a1, blsp_spi2,
blsp_uart2, blsp_uim2, blsp_i2c2, qdss_tracectl_a, sensor_int2,
blsp_spi5, blsp_uart5, ebi2_lcd, m_voc, sensor_int3, sensor_en,
blsp_i2c5, ebi2_a, qdss_tracedata_b, sensor_rst, blsp2_spi,
blsp_spi1, blsp_uart1, blsp_uim1, blsp3_spi, gcc_gp2_clk_b,
gcc_gp3_clk_b, blsp_i2c1, gcc_gp1_clk_b, blsp_spi4, blsp_uart4,
rcm_marker1, blsp_i2c4, qdss_cti_trig_out_a1, rcm_marker2,
qdss_cti_trig_out_a0, blsp_spi6, blsp_uart6, pri_mi2s_ws_a,
ebi2_lcd_te_b, blsp1_spi, backlight_en_b, pri_mi2s_data0_a,
pri_mi2s_data1_a, blsp_i2c6, ebi2_a_d_8_b, pri_mi2s_sck_a,
ebi2_lcd_cs_n_b, touch_rst, pri_mi2s_mclk_a, pwr_nav_enabled_a,
ts_int, sd_write, pwr_crypto_enabled_a, codec_rst, adsp_ext,
atest_combodac_to_gpio_native, uim2_data, gmac_mdio, gcc_gp1_clk_a,
uim2_clk, gcc_gp2_clk_a, eth_irq, uim2_reset, gcc_gp3_clk_a,
eth_rst, uim2_present, prng_rosc, uim1_data, uim1_clk,
uim1_reset, uim1_present, gcc_plltest, uim_batt, coex_uart,
codec_int, qdss_cti_trig_in_a0, atest_bbrx1, cri_trng0, atest_bbrx0,
cri_trng, qdss_cti_trig_in_b0, atest_gpsadc_dtest0_native,
qdss_cti_trig_out_b0, qdss_tracectl_b, qdss_traceclk_b, pa_indicator,
modem_tsync, nav_tsync_out_a, nav_ptp_pps_in_a, ptp_pps_out_a,
gsm0_tx, qdss_cti_trig_in_b1, cri_trng1, qdss_cti_trig_out_b1,
ssbi1, atest_gpsadc_dtest1_native, ssbi2, atest_char3, atest_char2,
atest_char1, atest_char0, atest_char, ebi0_wrcdc, ldo_update,
gcc_tlmm, ldo_en, dbg_out, atest_tsens, lcd_rst, wlan_en1,
nav_tsync_out_b, nav_ptp_pps_in_b, ptp_pps_out_b, pbs0, sec_mi2s,
pwr_modem_enabled_a, pbs1, pwr_modem_enabled_b, pbs2, pwr_nav_enabled_b,
pwr_crypto_enabled_b, gpio
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@01010000 {
compatible = "qcom,mdm9607-pinctrl";
reg = <0x01010000 0x300000>;
interrupts = <0 208 0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
qcom,tlmm-emmc-boot-select = <0x1>;
uart_console_active: uart_console_active {
mux {
pins = "gpio8", "gpio9";
function = "blsp_uart5";
};
config {
pins = "gpio8", "gpio9";
drive-strength = <2>;
bias-disable;
};
};
};

106
Documentation/devicetree/bindings/power/smb358-charger.txt Normal file
View File

@ -0,0 +1,106 @@
Summit smb358 battery charger
SMB358 is a single-cell battery charger. It can charge
the battery and power the system via the USB/AC adapter input.
The smb358 interface is via I2C bus.
Required Properties:
- compatible Must be "qcom,smb358-charger".
- reg The device 7-bit I2C address.
- interrupt-parent parent of interrupt.
- interrupts This indicates the IRQ number of the GPIO
connected to the STAT pin.
- qcom,irq-gpio GPIO which receives interrupts from STAT output.
- qcom,bms-psy-name This is a string and it points to the bms
power supply name.
- qcom,float-voltage-mv Float Voltage in mV - the maximum voltage up to which
the battery is charged. Supported range 3500mV to 4500mV
Optional Properties:
- qcom,fastchg-current-max-ma Fast Charging current in mA. Supported range is
from 200mA to 2000mA.
- qcom,chg-valid-gpio GPIO which indicates the charger presence.
This GPIO is connected to the SYSOK pin.
- qcom,chg-autonomous-mode This is a bool property and it indicates that the
charger is configured for autonomous operation and
does not require any software configuration.
- qcom,disable-apsd This is a bool property which disables automatic
power source detection (APSD). If this is set
charger detection is done by DCIN UV irq.
- qcom,charger-disabled This is a bool property which disables charging.
- qcom,using-pmic-therm This property indicates thermal pin connected to pmic or smb.
- qcom,vcc-i2c-supply Power source required to power up i2c bus.
- qcom,bms-controlled-charging This property indicates integrating with VMBMS, charger
driver and BMS communicates with each other via power_supply
framework. Property "qcom,iterm-disabled" also needs defined
if using this feature to make sure that the charger doesn't
terminate charging on its own.
- qcom,iterm-ma Specifies the termination current to indicate end-of-charge.
Possible values in mA - 30, 40, 60, 80, 100, 125, 150, 200.
- qcom,iterm-disabled Disables the termination current feature. This is a bool
property.
- qcom,recharge-mv Recharge threshold in mV - the offset from the float-volatge
as which the charger restarts charging. Possible
values are 50mV to 300mV.
- qcom,recharge-disabled Boolean value which disables the auto-recharge.
- qcom,chg-inhibit-disabled This is a bool property which disables charger inhibit.
Charger inhibit option prevents battery charging upon insertion
of the charger when battery voltage is above the programmed inhibit
threshold.
- qcom,chg-adc_tm phandle to the corresponding VADC device to read the ADC channels.
- qcom,cold-bat-decidegc Cold battery temperature in decidegC.
- qcom,hot-bat-decidegc Hot battery temperature in decidegC.
- qcom,bat-present-decidegc This is a property indicating battery present temperature, if
higher than it, battery should exist. Default value is negative,
if this property is 200, it stands for -200 decidegC.
- qcom,warm-bat-decidegc: Warm battery temperature in decidegC. After hitting this threshold,
"qcom,warm-bat-ma" defines maximum charging current and
"qcom,warm-bat-mv" defines maximum target voltage.
- qcom,cool-bat-decidegc: Cool battery temperature in decidegC. After hitting this threshold,
"qcom,cool-bat-ma" defines maximum charging current and
"qcom,cool-bat-mv" defines maximum target voltage.
- qcom,warm-bat-ma: Maximum warm battery charge current in milli-amps.
- qcom,cool-bat-ma: Maximum cool battery charge current in milli-amps.
- qcom,warm-bat-mv: Maximum warm battery target voltage in milli-volts.
- qcom,cool-bat-mv: Maximum cool battery target voltage in milli-volts.
- qcom,chg-vadc Corresponding VADC device's phandle.
- qcom,skip-usb-suspend-for-fake-battery: A boolean property to skip suspending USB path for fake
battery. If this property is not present then 'qcom,batt-id-vref-uv' and
'qcom,batt-id-rpullup-kohm' should be present.
- qcom,batt-id-vref-uv The reference voltage on the battery-ID line
specified in micro-volts.
- qcom,batt-id-rpullup-kohm The pull-up resistor connected on the battery-ID
(vref) line.
- qcom,using-vbat-sns Bool property to indicate that VBAT sense can be
done by PMIC.
Example:
i2c@f9967000 {
smb358-charger@1b {
compatible = "qcom,smb358-charger";
reg = <0x1b>;
interrupt-parent = <&msmgpio>;
interrupts = <17 0x0>;
qcom,irq-gpio = <&msmgpio 17 0x00>;
qcom,vcc-i2c-supply = <&pm8226_lvs1>;
qcom,float-voltage-mv = <4350>;
qcom,disable-apsd;
qcom,chg-inhibit-disabled;
qcom,bms-controlled-charging;
qcom,fastchg-current-max-ma = <1500>;
qcom,bms-psy-name = "bms";
qcom,chg-vadc = <&pm8226_vadc>;
qcom,chg-adc_tm = <&pm8226_adc_tm>;
qcom,hot-bat-decidegc = <500>;
qcom,cold-bat-decidegc = <0>;
qcom,bat-present-decidegc = <200>;
qcom,warm-bat-decidegc = <450>;
qcom,cool-bat-decidegc = <100>;
qcom,warm-bat-ma = <350>;
qcom,cool-bat-ma = <350>;
qcom,warm-bat-mv = <4200>;
qcom,cool-bat-mv = <4200>;
};
};

158
Documentation/devicetree/bindings/regulator/qpnp-regulator.txt Normal file
View File

@ -0,0 +1,158 @@
Qualcomm Technologies, Inc. QPNP Regulators
qpnp-regulator is a regulator driver which supports regulators inside of PMICs
that utilize the MSM SPMI implementation.
Required properties:
- compatible: Must be "qcom,qpnp-regulator"
- reg: Specifies the SPMI address and size for this regulator device
Note, this is the only property which can be used within a
subnode of a node which has specified spmi-dev-container.
- regulator-name: A string used as a descriptive name for regulator outputs
- parent-supply: phandle to the parent supply/regulator node
Required structure:
- A qcom,qpnp-regulator node must be a child of an SPMI node that has specified
the spmi-slave-container property
Optional properties:
- interrupts: List of interrupts used by the regulator.
- interrupt-names: List of strings defining the names of the
interrupts in the 'interrupts' property 1-to-1.
Supported values are "ocp" for voltage switch
type regulators. If an OCP interrupt is
specified, then the voltage switch will be
toggled off and back on when OCP triggers in
order to handle high in-rush current.
- qcom,system-load: Load in uA present on regulator that is not
captured by any consumer request
- qcom,enable-time: Time in us to delay after enabling the regulator
- qcom,auto-mode-enable: 1 = Enable automatic hardware selection of
regulator mode (HPM vs LPM); not available on
boost type regulators
0 = Disable auto mode selection
- qcom,bypass-mode-enable: 1 = Enable bypass mode for an LDO type regulator
so that it acts like a switch and simply outputs
its input voltage
0 = Do not enable bypass mode
- qcom,ocp-enable: 1 = Allow over current protection (OCP) to be
enabled for voltage switch type regulators so
that they latch off automatically when over
current is detected. OCP is enabled when in
HPM or auto mode.
0 = Disable OCP
- qcom,ocp-max-retries: Maximum number of times to try toggling a voltage
switch off and back on as a result of
consecutive over current events.
- qcom,ocp-retry-delay: Time to delay in milliseconds between each
voltage switch toggle after an over current
event takes place.
- qcom,pull-down-enable: 1 = Enable output pull down resistor when the
regulator is disabled
0 = Disable pull down resistor
- qcom,soft-start-enable: 1 = Enable soft start for LDO and voltage switch
type regulators so that output voltage slowly
ramps up when the regulator is enabled
0 = Disable soft start
- qcom,boost-current-limit: This property sets the current limit of boost
type regulators; supported values are:
0 = 300 mA
1 = 600 mA
2 = 900 mA
3 = 1200 mA
4 = 1500 mA
5 = 1800 mA
6 = 2100 mA
7 = 2400 mA
- qcom,pin-ctrl-enable: Bit mask specifying which hardware pins should be
used to enable the regulator, if any; supported
bits are:
0 = ignore all hardware enable signals
BIT(0) = follow HW0_EN signal
BIT(1) = follow HW1_EN signal
BIT(2) = follow HW2_EN signal
BIT(3) = follow HW3_EN signal
- qcom,pin-ctrl-hpm: Bit mask specifying which hardware pins should be
used to force the regulator into high power
mode, if any; supported bits are:
0 = ignore all hardware enable signals
BIT(0) = follow HW0_EN signal
BIT(1) = follow HW1_EN signal
BIT(2) = follow HW2_EN signal
BIT(3) = follow HW3_EN signal
BIT(4) = follow PMIC awake state
- qcom,vs-soft-start-strength: This property sets the soft start strength for
voltage switch type regulators; supported values
are:
0 = 0.05 uA
1 = 0.25 uA
2 = 0.55 uA
3 = 0.75 uA
- qcom,hpm-enable: 1 = Enable high power mode (HPM), also referred
to as NPM. HPM consumes more ground current
than LPM, but it can source significantly higher
load current. HPM is not available on boost
type regulators. For voltage switch type
regulators, HPM implies that over current
protection and soft start are active all the
time. This configuration can be overwritten
by changing the regulator's mode dynamically.
0 = Do not enable HPM
- qcom,force-type: Override the type and subtype register values. Useful for some
regulators that have invalid types advertised by the hardware.
The format is two unsigned integers of the form <type subtype>.
- spmi-dev-container: Specifies that all the device nodes specified
within this node should have their resources coalesced into a
single spmi_device. This is used to specify all SPMI peripherals
that logically make up a single regulator device.
Note, if a given optional qcom,* binding is not present, then the qpnp-regulator
driver will leave that feature in the default hardware state.
All properties specified within the core regulator framework can also be used.
These bindings can be found in regulator.txt.
Example:
qcom,spmi@fc4c0000 {
#address-cells = <1>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <3>;
qcom,pm8941@1 {
spmi-slave-container;
reg = <0x1>;
#address-cells = <1>;
#size-cells = <1>;
regulator@1400 {
regulator-name = "8941_s1";
spmi-dev-container;
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,qpnp-regulator";
reg = <0x1400 0x300>;
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1400000>;
qcom,ctl@1400 {
reg = <0x1400 0x100>;
};
qcom,ps@1500 {
reg = <0x1500 0x100>;
};
qcom,freq@1600 {
reg = <0x1600 0x100>;
};
};
regulator@4000 {
regulator-name = "8941_l1";
reg = <0x4000 0x100>;
compatible = "qcom,qpnp-regulator";
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1300000>;
qcom,pull-down-enable = <1>;
};
};
};

85
Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
View File

@ -2256,3 +2256,88 @@ Example:
asoc-codec = <&stub_codec>;
asoc-codec-names = "msm-stub-codec.1";
};
* MDM9607 ASoC Machine driver
Required properties:
- compatible : "qcom,mdm9607-audio-tomtom" for tomtom codec
"qcom,mdm9607-audio-tapan" for tapan codec
- qcom,model : The user-visible name of this sound card.
- qcom,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
the second being the connection's source.
- qcom,codec-mclk-clk-freq : Master clock value given to codec. Some WCD9XXX
codec can run at different mclk values. Mclk value can be 9.6MHz or 12.288MHz.
- asoc-platform: This is phandle list containing the references to platform device
nodes that are used as part of the sound card dai-links.
- asoc-platform-names: This property contains list of platform names. The order of
the platform names should match to that of the phandle order
given in "asoc-platform".
- asoc-cpu: This is phandle list containing the references to cpu dai device nodes
that are used as part of the sound card dai-links.
- asoc-cpu-names: This property contains list of cpu dai names. The order of the
cpu dai names should match to that of the phandle order given
in "asoc-cpu". The cpu names are in the form of "%s.%d" form,
where the id (%d) field represents the back-end AFE port id that
this CPU dai is associated with.
- asoc-codec: This is phandle list containing the references to codec dai device
nodes that are used as part of the sound card dai-links.
- asoc-codec-names: This property contains list of codec dai names. The order of the
codec dai names should match to that of the phandle order given
in "asoc-codec".
Optional Properties:
- qcom,mi2s-interface-mode: This property contains mi2s interface modes master/ slave.
Entry is a pair of strings, the first being for primary mi2s
and the second for secondary mi2s and so on
- qcom,auxpcm-interface-mode: This property contains auxpcm interface modes master/ slave.
Entry is a pair of strings, the first being for primary auxpcm
and the second for secondary auxpcm and so on
Example:
sound-9330 {
compatible = "qcom,mdm9607-audio-tomtom";
qcom,model = "mdm9607-tomtom-i2s-snd-card";
qcom,audio-routing =
"RX_BIAS", "MCLK",
"LDO_H", "MCLK",
"AMIC1", "MIC BIAS1 External",
"MIC BIAS1 External", "Handset Mic",
"AMIC2", "MIC BIAS2 External",
"MIC BIAS2 External", "Headset Mic",
"AMIC3", "MIC BIAS2 External",
"MIC BIAS2 External", "ANCRight Headset Mic",
"AMIC4", "MIC BIAS2 External",
"MIC BIAS2 External", "ANCLeft Headset Mic",
"DMIC1", "MIC BIAS1 External",
"MIC BIAS1 External", "Digital Mic1",
"DMIC3", "MIC BIAS3 External",
"MIC BIAS3 External", "Digital Mic3";
qcom,tomtom-mclk-clk-freq = <12288000>;
qcom,mi2s-interface-mode = "pri_mi2s_master", "sec_mi2s_master";
qcom,auxpcm-interface-mode = "pri_pcm_master", "sec_pcm_master";
asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>,
<&loopback>, <&hostless>, <&afe>, <&routing>,
<&pcm_dtmf>, <&host_pcm>;
asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
"msm-voip-dsp", "msm-pcm-voice", "msm-pcm-loopback",
"msm-pcm-hostless", "msm-pcm-afe",
"msm-pcm-routing", "msm-pcm-dtmf", "msm-voice-host-pcm";
asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&dtmf_tx>,
<&rx_capture_tx>, <&rx_playback_rx>,
<&tx_capture_tx>, <&tx_playback_rx>,
<&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>,
<&afe_proxy_tx>, <&incall_record_rx>,
<&incall_record_tx>, <&incall_music_rx>;
asoc-cpu-names = "msm-dai-q6-auxpcm.1", "msm-dai-q6-mi2s.0",
"msm-dai-stub-dev.4", "msm-dai-stub-dev.5",
"msm-dai-stub-dev.6", "msm-dai-stub-dev.7",
"msm-dai-stub-dev.8", "msm-dai-q6-dev.224",
"msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
"msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
"msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773";
asoc-codec = <&stub_codec>;
asoc-codec-names = "msm-stub-codec.1";
};

171
Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt Normal file
View File

@ -0,0 +1,171 @@
Qualcomm Technologies, Inc. QPNP PMIC thermal monitor ADC driver (VADC_TM)
QPNP PMIC thermal monitoring (TM) provides interface to thermal clients
to set temperature thresholds and receive notification when the thresholds
are crossed. A 15 bit ADC is used for measurements. The driver is part
of the sysfs thermal framework that provides support to read the trip
points, set threshold for the trip points and enable the trip points.
Separate kernel api's are provided to usb_id and batt_therm
to set thresholds and receive threshold notifications.
VADC_TM node
Required properties:
- compatible : should be "qcom,qpnp-adc-tm" for thermal ADC driver.
- reg : offset and length of the PMIC Aribter register map.
- address-cells : Must be one.
- size-cells : Must be zero.
- interrupts : The thermal ADC bank peripheral interrupts for eoc, high and low interrupts.
- interrupt-names : Should be "eoc-int-en-set", "high-thr-en-set" and "low-thr-en-set".
- qcom,adc-bit-resolution : Bit resolution of the ADC.
- qcom,adc-vdd-reference : Voltage reference used by the ADC.
Optional properties:
- qcom,thermal-node : If present a thermal node is created and the channel is registered as
part of the thermal sysfs which allows clients to use the thermal framework
to set temperature thresholds and receive notification when the temperature
crosses a set threshold, read temperature and enable/set trip types supported
by the thermal framework.
- qcom,meas-interval-timer-idx: If present select from the following timer index to choose
a preset configurable measurement interval timer value. The driver defaults
to timer 2 with a measurement interval of 1 second if the property is not present.
0 : Select Timer 1 for a measurement polling interval of 3.9 milliseconds.
1 : Select Timer 2 for a measurement polling interval of 1 second.
2 : Select Timer 3 for a measurement polling interval of 4 seconds.
- qcom,adc-tm-recalib-check: Add this property to check if recalibration required due to inaccuracy.
- hkadc_ldo-supply : Add this property if VADC needs to perform a Software Vote for the HKADC.
- hkadc_ok-supply : Add this property if the VADC needs to perform a Software vote for the HKADC VREG_OK.
Client required property:
- qcom,<consumer name>-adc_tm : The phandle to the corresponding adc_tm device.
The consumer name passed to the driver when calling
qpnp_get_adc_tm() is used to associate the client
with the corresponding device.
Channel nodes
NOTE: Atleast one Channel node is required.
Required properties:
- label : Channel name used for sysfs entry.
- reg : AMUX channel number.
- qcom,decimation : Sampling rate to use for the individual channel measurement.
Select from the following unsigned int.
0 : 512
1 : 1K
2 : 2K
3 : 4K
- qcom,pre-div-channel-scaling : Pre-div used for the channel before the signal is being measured.
Select from the following unsigned int for the corresponding
numerator/denominator pre-div ratio.
0 : pre-div ratio of {1, 1}
1 : pre-div ratio of {1, 3}
2 : pre-div ratio of {1, 4}
3 : pre-div ratio of {1, 6}
4 : pre-div ratio of {1, 20}
5 : pre-div ratio of {1, 8}
6 : pre-div ratio of {10, 81}
7 : pre-div ratio of {1, 10}
- qcom,calibration-type : Reference voltage to use for channel calibration.
Channel calibration is dependendent on the channel.
Certain channels like XO_THERM, BATT_THERM use ratiometric
calibration. Most other channels fall under absolute calibration.
Select from the following strings.
"absolute" : Uses the 625mv and 1.25V reference channels.
"ratiometric" : Uses the reference Voltage/GND for calibration.
- qcom,scale-function : Reverse scaling function used to convert raw ADC code to units specific to
a given channel.
Select from the following unsigned int.
0 : Scaling to convert voltage in uV to raw adc code.
1 : Scaling to convert decidegC to raw adc code.
2 : Scaling for converting USB_ID reverse scaling.
3 : Scaling to convert milldegC to raw ADC code.
4 : Scaling to convert smb_batt_therm values to raw ADC code.
5 : Scaling to perform reverse calibration for absolute voltage from uV
to raw ADC code.
6 : Scaling to convert qrd skuh battery decidegC to raw ADC code.
- qcom,hw-settle-time : Settling period for the channel before ADC read.
Select from the following unsigned int.
0 : 0us
1 : 100us
2 : 200us
3 : 300us
4 : 400us
5 : 500us
6 : 600us
7 : 700us
8 : 800us
9 : 900us
0xa : 1ms
0xb : 2ms
0xc : 4ms
0xd : 6ms
0xe : 8ms
0xf : 10ms
- qcom,fast-avg-setup : Average number of samples to be used for measurement. Fast averaging
provides the option to obtain a single measurement from the ADC that
is an average of multiple samples. The value selected is 2^(value)
Select from
0 : 1
1 : 2
2 : 4
3 : 8
4 : 16
5 : 32
6 : 64
7 : 128
8 : 256
- qcom,btm-channel-number : Depending on the PMIC version, a max of upto 8 BTM channels.
The BTM channel numbers are statically allocated to the
corresponding channel node.
- qcom,adc_tm-vadc : phandle to the corresponding VADC device to read the ADC channels.
Client device example:
/* Add to the clients node that needs the ADC_TM channel A/D */
client_node {
qcom,client-adc_tm = <&pm8941_adc_tm>;
};
Example:
/* Main Node */
qcom,vadc@3400 {
compatible = "qcom,qpnp-adc-tm";
reg = <0x3400 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x0 0x34 0x0>,
<0x0 0x34 0x3>,
<0x0 0x34 0x4>;
interrupt-names = "eoc-int-en-set",
"high-thr-en-set",
"low-thr-en-set";
qcom,adc-bit-resolution = <15>;
qcom,adc-vdd-reference = <1800>;
qcom,adc_tm-vadc = <&pm8941_vadc>;
/* Channel Node to be registered as part of thermal sysfs */
chan@b5 {
label = "pa_therm1";
reg = <0xb5>;
qcom,decimation = <0>;
qcom,pre-div-channel-scaling = <0>;
qcom,calibration-type = "absolute";
qcom,scale-function = <2>;
qcom,hw-settle-time = <0>;
qcom,fast-avg-setup = <0>;
qcom,btm-channel-number = <0x70>;
qcom,thermal-node;
};
/* Channel Node */
chan@6 {
label = "vbat_sns";
reg = <6>;
qcom,decimation = <0>;
qcom,pre-div-channel-scaling = <1>;
qcom,calibration-type = "absolute";
qcom,scale-function = <3>;
qcom,hw-settle-time = <0>;
qcom,fast-avg-setup = <0>;
qcom,btm-channel-number = <0x78>;
};
};

1
Documentation/devicetree/bindings/thermal/tsens.txt
View File

@ -22,6 +22,7 @@ Required properties:
should be "qcom,msm8937-tsens" for 8937 TSENS driver.
should be "qcom,qcs405-tsens" for QCS405 TSENS driver.
should be "qcom,sm6150-tsens" for 6150 TSENS driver.
should be "qcom,mdm9607-tsens" for 9607 TSENS driver.
The compatible property is used to identify the respective controller to use
for the corresponding SoC.

84
Documentation/devicetree/bindings/tty/serial/msm_serial.txt Normal file
View File

@ -0,0 +1,84 @@
* Qualcomm Technologies, Inc. MSM UART
Required properties:
- compatible :
- "qcom,msm-uart", and one of "qcom,msm-hsuart" or
"qcom,msm-lsuart".
- reg : offset and length of the register set for the device
for the hsuart operating in compatible mode, there should be a
second pair describing the gsbi registers.
- interrupts : should contain the uart interrupt.
There are two different UART blocks used in MSM devices,
"qcom,msm-hsuart" and "qcom,msm-lsuart". The msm-serial driver is
able to handle both of these, and matches against the "qcom,msm-uart"
as the compatibility.
The registers for the "qcom,msm-hsuart" device need to specify both
register blocks, even for the common driver.
Example:
uart@19c400000 {
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
reg = <0x19c40000 0x1000>,
<0x19c00000 0x1000>;
interrupts = <195>;
};
* Qualcomm Technologies, Inc. MSM HSUART
Required properties:
- compatible : one of:
- "qcom,msm-lsuart-v14"
- reg : offset and length of the register set for the device.
- interrupts : should contain the uart interrupt.
Optional properties:
- qcom,config-gpio : Set this value if UART GPIOs need to be configured by driver.
set 4 if 4-wire UART used (for Tx, Rx, CTS, RFR GPIOs).
Set 1 if 2-wire UART used (for Tx, Rx GPIOs).
- qcom,<gpio-name>-gpio : handle to the GPIO node, see "gpios property" in
Documentation/devicetree/bindings/gpio/gpio.txt.
"gpio-name" can be "tx", "rx", "cts" and "rfr" based on number of UART GPIOs
need to configured.
qcom,use-pm : If present, this property will cause the device to prevent system
suspend as long as the port remains open.
- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for below properties:
- qcom,msm_bus,name
- qcom,msm_bus,num_cases
- qcom,msm_bus,active_only
- qcom,msm_bus,num_paths
- qcom,msm_bus,vectors
Aliases:
An alias may optionally be used to bind the serial device to a tty device
(ttyHSLx) with a given line number. Aliases are of the form serial<n> where <n>
is an integer representing the line number to use. On systems with multiple
serial devices present it is recommended that an alias be defined for each such
device.
Example:
aliases {
serial0 = &uart0; // This device will be called ttyHSL0
};
uart0: serial@19c400000 {
compatible = "qcom,msm-lsuart-v14"
reg = <0x19c40000 0x1000">;
interrupts = <195>;
qcom,config-gpio = <4>;
qcom,tx-gpio = <&msmgpio 41 0x00>;
qcom,rx-gpio = <&msmgpio 42 0x00>;
qcom,cts-gpio = <&msmgpio 43 0x00>;
qcom,rfr-gpio = <&msmgpio 44 0x00>;
qcom,use-pm;
qcom,msm-bus,name = "serial_uart0";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<84 512 0 0>,
<84 512 500 800>;
};

36
Documentation/devicetree/bindings/usb/msm-android-usb.txt Normal file
View File

@ -0,0 +1,36 @@
ANDROID USB:
This describes the device tree node for the Android USB gadget device.
This works in conjunction with a USB Device Controller (UDC) to provide
a dynamically configurable composition of functions to be exposed when
connected to a USB host.
Required properties:
- compatible: should be "qcom,android-usb"
Optional properties :
- reg : offset and length of memory region that is used by device to
update USB PID and serial numbers used by bootloader in DLOAD mode.
- qcom,pm-qos-latency : This property must be a list of three integer values
(perf, normal, sleep) where each value respresents DMA latency in microsecs.
First value represents DMA latency to vote with pm_qos when back to back USB
transfers are happening and it requires USB thoughput to be maximum.
Second value represents value to vote when not many USB transfers are
happening and it is OK to have higher DMA latency to save power.
Third value represents DMA latency to vote when USB BUS is IDLE and absolutely
no transfers are happening. It should allow transition to lowest power state.
- qcom,usb-core-id: Index to refer USB hardware core to bind android gadget driver
with UDC if multiple USB peripheral controllers are present. If unspecified,
core is set to zero by default.
- qcom,supported-func: Represents list of supported function drivers. If this
property is present android USB driver dynamically creats the list of
supported function drivers and uses this list instead of statically defined default
supported function driver list.
Example Android USB device node :
android_usb@fc42b0c8 {
compatible = "qcom,android-usb";
reg = <0xfc42b0c8 0xc8>;
qcom,pm-qos-latency = <2 1001 12701>;
qcom,supported-func = "rndis_gsi","ecm_gsi","rmnet_gsi";
qcom,usb-core-id = <1>;
};

216
Documentation/devicetree/bindings/usb/msm-ehci-hsic.txt Normal file
View File

@ -0,0 +1,216 @@
MSM HSIC EHCI controller
Required properties :
- compatible : should be "qcom,hsic-host"
- regs : offset and length of the register set in the memory map
- interrupts: IRQ lines used by this controller
- interrupt-names : Required interrupt resource entries are:
"core_irq" : Interrupt for HSIC core
- <supply-name>-supply: handle to the regulator device tree node
Required "supply-name" is either "hsic_vdd_dig" or "HSIC_VDDCX" and
optionally - "HSIC_GDSC".
Optional properties :
- interrupt-parent - This must provide reference to the current
device node.
- #address-cells - Should provide a value of 0.
- interrupts - Should be <0 1 2> and it is an index to the
interrupt-map.
- #interrupt-cells - should provide a value of 1.
- #interrupt-mask - should provide a value of 0xffffffff.
- interrupt-map - Must create mapping for the number of interrupts
that are defined in above interrupts property.
For HSIC device node, it should define 3 mappings for
core_irq, async_irq and wakeup in the format
mentioned in below example node of HSIC.
- interrupt-names : Optional interrupt resource entries are:
"async_irq" : Interrupt from HSIC for asynchronous events in HSIC LPM.
"wakeup" : Wakeup interrupt from HSIC during suspend (or XO shutdown).
- pinctrl-names : This should be defined if a target uses pinctrl framework.
See "pinctrl" in Documentation/devicetree/bindings/pinctrl/msm-pinctrl.txt.
It should specify the names of the configs that pinctrl can install in driver
Following are the pinctrl configs that can be installed
"hsic_ehci_active" : Active configuration of pins, this should specify active
config defined in pin groups of used gpio's from strobe, data and
resume.
"hsic_ehci_sleep" : Disabled configuration of pins, this should specify sleep
config defined in pin groups of used gpio's from strobe, data and
resume.
- hsic,<gpio-name>-gpio : handle to the GPIO node, see "gpios property"
in Documentation/devicetree/bindings/gpio/gpio.txt.
If pinctrl is being used we need to define only gpio's which drives signals
using gpiolib api's like resume gpio in dt, the node name in such cases should
be msm_gpio as defined in pinctrl-dtsi. For gpio's only installing active and
sleep configs it is not required to specify the gpio in dt file.
Optional "gpio-name" can be "strobe", "data" and "resume".
- hsic,resume-gpio : if present then periperal connected to hsic controller
cannot wakeup from XO shutdown using in-band hsic resume. Use resume
gpio to wakeup peripheral
- qcom,phy-sof-workaround : If present then HSIC PHY has h/w BUGs related to
SOFs. All the relevant software workarounds are required for the same during
suspend, reset and resume.
- qcom,phy-susp-sof-workaround : If present then HSIC PHY has h/w BUG related to
SOFs while entering SUSPEND. Relevant software workaround is required for the same
during SUSPEND.
- qcom,phy-reset-sof-workaround : If present then HSIC PHY has h/w BUG related to
SOFs during RESET.
- qcom,pool-64-bit-align: If present then the pool's memory will be aligned
to 64 bits
- qcom,enable_hbm: if present host bus manager is enabled.
- qcom,disable-park-mode: if present park mode is enabled. Park mode enables executing
up to 3 usb packets from each QH.
- hsic,consider-ipa-handshake: If present then hsic low power mode is
depend on suitable handshake with the IPA peer.
- qcom,ahb-async-bridge-bypass: if present AHB ASYNC bridge will be bypassed such that
the bridge on the slave AHB is always used.
- hsic,log2-itc: itc (interrupt threshold control) defines rate at which usb
controller will issue interrupts. It represents max interrupt interval
measured in micro frames. In high speed USB, each micro frame is 125us.
Valid values are from zero to six. Zero is default. Higher ITC value will
result in higher interrupt latency and can impact overall data latency.
log2-itc - Max interrupt threshold
-------- -----------------------
0 (2^0 = 1) 1 micro frame interrupt threshold aka 125us interrupt threshold
1 (2^1 = 2) 2 micro frame interrupt threshold aka 250us interrupt threshold
2 (2^2 = 4) 4 micro frame interrupt threshold aka 500us interrupt threshold
3 (2^3 = 8) 8 micro frame interrupt threshold aka 1ms interrupt threshold
4 (2^4 = 16) 16 micro frame interrupt threshold aka 2ms interrupt threshold
5 (2^5 = 32) 32 micro frame interrupt threshold aka 4ms interrupt threshold
6 (2^6 = 64) 64 micro frame interrupt threshold aka 8ms interrupt threshold
- hsic,disable-cerr: CERR is 2bit down error counter that keeps track of number
of consecutive errors detected on single usb transaction. When set to non
zero value, hw decrements the count and updates qTD when transaction fails.
If counter reaches zero, hw marks the qTD inactive and triggers the interrupt.
When CERR is programmed to zero, hw ignores transaction failures. ECHI stack
programs the CERR to 3 by default. When this flag is true, CERR is set to
zero and transaction errors are ignored.
- hsic,reset-delay: If present then add the given delay time (ms) between
the reset and enumeration. Since some devices might take more than 100ms
for initialization when receiving the bus reset, add delay to avoid the
problem that enmueration is before device initialization done.
- hsic,vdd-voltage-level: This property must be a list of three integer
values (no, min, max) where each value represents either a voltage in
microvolts or a value corresponding to voltage corner
- qcom,disable-internal-clk-gating: If present then internal clock gating in
controller is disabled. Internal clock gating is enabled by default in hw.
- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
below optional properties:
- qcom,msm_bus,name
- qcom,msm_bus,num_cases
- qcom,msm_bus,num_paths
- qcom,msm_bus,vectors
Example MSM HSIC EHCI controller device node :
hsic_host: hsic@f9a15000 {
compatible = "qcom,hsic-host";
reg = <0xf9a15000 0x400>;
#address-cells = <0>;
interrupt-parent = <&hsic_host>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 136 0
1 &intc 0 148 0
2 &msm_gpio 144 0x8>;
interrupt-names = "core_irq", "async_irq", "wakeup";
hsic_vdd_dig-supply = <&pm8841_s2_corner>;
HSIC_GDSC-supply = <&gdsc_usb_hsic>;
/* If pinctrl is used and resume gpio is present */
pinctrl-names = "hsic_ehci_active","hsic_ehci_sleep";
pinctrl-0 = <&hsic_act &resume_act>;
pinctrl-1 = <&hsic_sus &resume_act>;
hsic,resume-gpio = <&msm_gpio 80 0x00>;
/* else (pinctrl is not present) */
hsic,strobe-gpio = <&msmgpio 144 0x00>;
hsic,data-gpio = <&msmgpio 145 0x00>;
hsic,resume-gpio = <&msmgpio 80 0x00>;
/* End */
hsic,ignore-cal-pad-config;
hsic,strobe-pad-offset = <0x2050>;
hsic,data-pad-offset = <0x2054>;
hsic,consider-ipa-handshake;
hsic,vdd-voltage-level = <1 5 7>;
qcom,msm-bus,name = "hsic";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<85 512 0 0>,
<85 512 40000 160000>;
};
SMSC HSIC HUB
Required properties :
- compatible : should be "qcom,hsic-smsc-hub"
- smsc,model-id : should be <3502>/<3503>/<4604> depending on hub model. It
will be 0 for standalone HSIC controller configuration.
- smsc,reset-gpio: this output gpio is used to assert/de-assert the hub reset
- Sub node for "MSM HSIC EHCI controller".
Sub node has the required properties mentioned above.
Optional properties :
- pinctrl-names : This should be defined if a target uses pinctrl framework.
See "pinctrl" in Documentation/devicetree/bindings/pinctrl/msm-pinctrl.txt.
It should specify the names of the configs that pinctrl can install in driver
Following are the pinctrl configs that can be installed
"smsc_active" : Active configuration of pins, this should specify active
config defined in pin groups of used gpio's from reset, refclk, xo-clk
and int.
"smsc_sleep" : Disabled configuration of pins, this should specify the sleep
config defined in pin groups of used gpio's from reset, refclk, xo-clk
and int.
If pinctrl is being used we need to only define gpio's which drives signals
using gpiolib api's like reset and xo-clk gpio in dt, the node name in such
cases should be msm_gpio as defined in pinctrl-dtsi. For gpio's only
installing active and sleep configs it is not required to specify the gpio
in dt file.
- smsc,int-gpio: this input gpio indicate HUB suspend status and signal remote
wakeup interrupt
- smsc,refclk-gpio: this gpio is used to supply the reference clock
- smsc,xo-clk-gpio: this output gpio is used to control the external XO clock
which is supplied to the hub as a reference clock
- hub-vbus-supply: this regulator is used to supply the power to
downstream ports
- hub-int-supply: this regulator is used to bias the interrupt gpio
- ext-hub-vddio-supply: this regulator is used to supply the power to one of
the hub's VDD.
Example SMSC HSIC HUB :
hsic_hub {
compatible = "qcom,hsic-smsc-hub";
smsc,model-id = <4604>;
ranges;
/* If pinctrl is used with all gpio_present */
pinctrl-names = "smsc_active","smsc_sleep";
pinctrl-0 = <&reset_act &refclk_act &int_act>;
pinctrl-1 = <&reset_sus &refclk_sus &int_sus>;
smsc,reset-gpio = <&pm8941_gpios 8 0x00>;
/* If target does not use pinctrl */
smsc,reset-gpio = <&pm8941_gpios 8 0x00>;
smsc,refclk-gpio = <&pm8941_gpios 16 0x00>;
smsc,int-gpio = <&msmgpio 50 0x00>;
/* End if */
hub-int-supply = <&pm8941_l10>;
hub-vbus-supply = <&pm8941_mvs1>;
hsic@f9a00000 {
compatible = "qcom,hsic-host";
reg = <0xf9a00000 0x400>;
interrupts = <0 136 0>;
interrupt-names = "core_irq";
HSIC_VDDCX-supply = <&pm8841_s2>;
HSIC_GDSC-supply = <&gdsc_usb_hsic>;
hsic,strobe-gpio = <&msmgpio 144 0x00>;
hsic,data-gpio = <&msmgpio 145 0x00>;
hsic,ignore-cal-pad-config;
hsic,strobe-pad-offset = <0x2050>;
hsic,data-pad-offset = <0x2054>;
};
};

37
Documentation/devicetree/bindings/usb/msm-hsic-peripheral.txt Normal file
View File

@ -0,0 +1,37 @@
USB HSIC Peripheral:
This describes device tree node for the USB HSIC Peripheral. This works with
usage of USB Device controller to enable USB HSIC Device mode functionality.
Required properties:
- compatible: should be "qcom,hsic-peripheral"
- regs : offset and length of the register set in the memory map
- interrupts: IRQ lines used by this controller
- <supply-name>-supply: handle to the regulator device tree node
Required "supply-name" is "vdd" and optional "GDSC".
- qcom,vdd-voltage-level: This property must be a list of three integer
values (no, min, max) where each value represents either a voltage in
microvolts or a value corresponding to voltage corner.
Optional properties :
- qcom,usb-id-core: USB Core Index to be used to bind with gadget driver.
- qcom,hsic-tlmm-init-seq: HSIC TLMM PADS initialization sequence with
reg, value pairs.
- reg : offset and length of the register set in the memory map.
This is required if 'qcom,hsic-tlmm-init-seq' is specified.
- qcom,hsic-disable-on-boot: If present then HSIC is suspended on bootup
and user can enable this using sysfs if HSIC host is present.
Example USB HSIC device node :
hsic: hsic@f9a15000 {
compatible = "qcom,hsic-peripheral";
reg = <0xf9a15000 0x352>,
<0x01112000 0xc>;
interrupts = <0 136 0>;
qcom,usb-id-core = <1>;
vdd-supply = <&pmd9635_l2>;
GDSC-supply = <&gdsc_usb_hsic>;
qcom,vdd-voltage-level = <0 1200000 1200000>;
qcom,hsic-tlmm-init-seq =
<0x8 0x5 0x4 0x5 0x0 0x1>;
qcom,hsic-disable-on-boot;
};

231
Documentation/devicetree/bindings/usb/msm-hsusb.txt
View File

@ -108,3 +108,234 @@ Example HSUSB OTG controller device node:
qcom,phy-init-sequence = < -1 0x63 >;
qcom,vdd-levels = <1 5 7>;
};
OTG:
Required properties :
- compatible : should be "qcom,hsusb-otg"
- regs : Array of offset and length of the register sets in the memory map
- reg-names : indicates various iomem resources passed by name. The possible
strings in this field are:
"core": USB controller register space. (Required)
"tcsr": TCSR register for routing USB Controller signals to
either picoPHY0 or picoPHY1. (Optional)
"phy_csr": PHY Wrapper CSR register space. Provides register level
interface through AHB2PHY for performing PHY related operations
like retention and HV interrupts management.
- interrupts: IRQ line
- interrupt-names: OTG interrupt name(s) referenced in interrupts above
HSUSB OTG expects "core_irq" which is IRQ line from CORE and
"async_irq" from HSPHY for asynchronous wakeup events in LPM.
optional ones are described in next section.
- qcom,hsusb-otg-phy-type: PHY type can be one of
1 - Chipidea PHY (obsolete)
2 - Synopsis Pico PHY
3 - Synopsis Femto PHY
4 - QUSB ULPI PHY
- qcom,hsusb-otg-mode: Operational mode. Can be one of
1 - Peripheral only mode
2 - Host only mode
3 - OTG mode
Based on the mode, OTG driver registers platform devices for
gadget and host.
- qcom,hsusb-otg-otg-control: OTG control (VBUS and ID notifications)
can be one of
1 - PHY control
2 - PMIC control
3 - User control (via debugfs)
- <supply-name>-supply: handle to the regulator device tree node
Required "supply-name" is "HSUSB_VDDCX" (when voting for VDDCX) or
"hsusb_vdd_dig" (when voting for VDDCX Corner voltage),
"HSUSB_1p8-supply" and "HSUSB_3p3-supply".
- qcom,vdd-voltage-level: This property must be a list of three integer
values (none, min, max) where each value represents either a voltage
in microvolts or a value corresponding to voltage corner. If usb core
supports svs, min value will have absolute SVS or SVS corner otherwise
min value will have absolute nominal or nominal corner.
- clocks: a list of phandles to the USB clocks. Usage is as per
Documentation/devicetree/bindings/clock/clock-bindings.txt
- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
property.
Required clocks:
"core_clk": USB core clock that is required for data transfers.
"iface_clk": USB core clock that is required for register access.
Optional clocks:
"sleep_clk": PHY sleep clock. Required for interrupts.
"phy_reset_clk": PHY blocks asynchronous reset clock. Required
for the USB block reset. It is a reset only clock.
"phy_por_clk": Reset only clock for asserting/de-asserting
PHY POR signal. Required for overriding PHY parameters.
"phy_csr_clk": Required for accessing PHY CSR registers through
AHB2PHY interface.
"phy_ref_clk": Required when PHY have referance clock,
"xo": XO clock. The source clock that is used as a reference clock
to the PHY.
"bimc_clk", "snoc_clk", "pcnoc_clk": bus voting clocks. Used to
keep buses at a nominal frequency during USB peripheral
mode for achieving max throughput.
- qcom,max-nominal-sysclk-rate: Indicates maximum nominal frequency for which
system clock should be voted whenever streaming mode is enabled.
Optional properties :
- interrupt-names : Optional interrupt resource entries are:
"pmic_id_irq" : Interrupt from PMIC for external ID pin notification.
"phy_irq" : Interrupt from PHY. Used for ID detection.
- qcom,hsusb-otg-disable-reset: If present then core is RESET only during
init, otherwise core is RESET for every cable disconnect as well
- qcom,hsusb-otg-pnoc-errata-fix: If present then workaround for PNOC
performance issue is applied which requires changing the mem-type
attribute via VMIDMT.
- qcom,hsusb-otg-default-mode: The default USB mode after boot-up.
Applicable only when OTG is controlled by user. Can be one of
0 - None. Low power mode
1 - Peripheral
2 - Host
- qcom,hsusb-otg-phy-init-seq: PHY configuration sequence. val, reg pairs
terminate with -1
- qcom,hsusb-otg-power-budget: VBUS power budget in mA
0 will be treated as 500mA
- qcom,hsusb-otg-pclk-src-name: The source of pclk
- Refer to "Documentation/devicetree/bindings/arm/msm/msm-bus.txt" for
below optional properties:
- qcom,msm-bus,name
- qcom,msm-bus,num_cases - There are three valid cases for this: NONE, MAX
and MIN bandwidth votes. Minimum two cases must be defined for
both NONE and MAX votes. If MIN vote is different from NONE VOTE
then specify third case for MIN VOTE. If explicit NOC clock rates
are not specified then MAX value should be large enough to get
desired BUS frequencies. In case explicit NOC clock rates are
specified, peripheral mode bus bandwidth vote should be defined
to vote for arbitrated bandwidth so that 60MHz frequency is met.
- qcom,msm-bus,num_paths
- qcom,msm-bus,vectors
- qcom,hsusb-otg-lpm-on-dev-suspend: If present then USB enter to
low power mode upon receiving bus suspend.
- qcom,hsusb-otg-clk-always-on-workaround: If present then USB core clocks
remain active upon receiving bus suspend and USB cable is connected.
Used for allowing USB to respond for remote wakup.
- qcom,hsusb-otg-delay-lpm: If present then USB core will wait one second
after disconnect before entering low power mode.
- <supply-name>-supply: handle to the regulator device tree node.
Optional "supply-name" is "vbus_otg" to supply vbus in host mode.
- qcom,dp-manual-pullup: If present, vbus is not routed to USB controller/phy
and controller driver therefore enables pull-up explicitly before
starting controller using usbcmd run/stop bit.
- qcom,usb2-enable-hsphy2: If present then USB2 controller is connected to 2nd
HSPHY.
- qcom,hsusb-log2-itc: value of 2^(log2_itc-1) will be used as the
interrupt threshold (ITC), when log2_itc is between 1 to 7.
- qcom,hsusb-l1-supported: If present, the device supports l1 (Link power
management).
- qcom,no-selective-suspend: If present selective suspend is disabled on hub ports.
- qcom,hsusb-otg-mpm-dpsehv-int: If present, indicates mpm interrupt to be
configured for detection of dp line transition during VDD minimization.
- qcom,hsusb-otg-mpm-dmsehv-int: If present, indicates mpm interrupt to be
configured for detection of dm line transition during VDD minimization.
- pinctrl-names : This should be defined if a target uses gpio and pinctrl framework.
See "pinctrl" in Documentation/devicetree/bindings/pinctrl/msm-pinctrl.txt.
It should specify the names of the configs that pinctrl can install in driver
Following are the pinctrl config that can be installed
"hsusb_active" : Active configuration of pins, this should specify active
config of vddmin gpio (if used) defined in their pin groups.
"hsusb_sleep" : Disabled configuration of pins, this should specify sleep
config of vddmin gpio (if used) defined in their pin groups.
- qcom,hsusb-otg-vddmin-gpio = If present, indicates a gpio that will be used
to supply voltage to the D+ line during VDD minimization and peripheral
bus suspend. If not exists, then VDD minimization will not be allowed
during peripheral bus suspend.
- qcom,ahb-async-bridge-bypass: If present, indicates that enable AHB2AHB By Pass
mode with device controller for better throughput. With this mode, USB Core
runs using PNOC clock and synchronous to it. Hence it is must to have proper
"qcom,msm-bus,vectors" to have high bus frequency. User shouldn't try to
enable this feature without proper bus voting. When this feature is enabled,
it is required to do HW reset during cable disconnect for host mode functionality
working and hence need to disable qcom,hsusb-otg-disable-reset. With this feature
enabled, USB HW has to vote for maximum PNOC frequency as USB HW cannot tolerate
changes in PNOC frequency which results in USB functionality failure.
- qcom,disable-retention-with-vdd-min: If present don't allow phy retention but allow
vdd min.
- qcom,usbin-vadc: Corresponding vadc device's phandle to read usbin voltage using VADC.
This will be used to get value of usb power supply's VOLTAGE_NOW property.
- qcom,usbid-gpio: This corresponds to gpio which is used for USB ID detection.
- qcom,hub-reset-gpio: This corresponds to gpio which is used for HUB reset.
- qcom,sw-sel-gpio: This corresponds to gpio which is used for switch select routing
of D+/D- between the USB HUB and type B USB jack for peripheral mode.
- qcom,bus-clk-rate: If present, indicates nominal bus frequency to be voted for
bimc/snoc/pcnoc clock with usb cable connected. If AHB2AHB bypass is enabled,
pcnoc value should be defined to very large number so that PNOC runs at max
frequency. If 'qcom,default-mode-svs' is also set then two set of frequencies
must be specified for SVS and NOM modes which user can change using sysfs node.
- qcom,phy-dvdd-always-on: If present PHY DVDD is supplied by a always-on
regulator unlike vddcx/vddmx. PHY can keep D+ pull-up and D+/D-
pull-down resistors during peripheral and host bus suspend without
any re-work.
- qcom,emulation: Indicates that we are running on emulation platform.
- qcom,boost-sysclk-with-streaming: If present, enable controller specific
streaming feature. Also this flag can bump up usb system clock to max in streaming
mode. This flag enables streaming mode for all compositions and is different from
streaming-func property defined in android device node. Please refer Doumentation/
devicetree/bindings/usb/android-dev.txt for details about "streaming-func" property.
- qcom,axi-prefetch-enable: If present, AXI64 interface will be used for transferring data
to/from DDR by controller.
- qcom,enable-sdp-typec-current-limit: Indicates whether type-c current for SDP CHARGER to
be limited.
- qcom,enable-phy-id-pullup: If present, PHY can keep D+ pull-up resistor on USB ID line
during cable disconnect.
- qcom,max-svs-sysclk-rate: Indicates system clock frequency voted by driver in
non-perf mode. In perf mode driver uses qcom,max-nominal-sysclk-rate.
- qcom,pm-qos-latency: This represents max tolerable CPU latency in microsecs,
which is used as a vote by driver to get max performance in perf mode.
- qcom,default-mode-svs: Indicates USB system clock should run at SVS frequency.
User can bump it up using 'perf_mode' sysfs attribute for gadget.
- qcom,vbus-low-as-hostmode: If present, specifies USB_VBUS to switch to host mode
if USB_VBUS is low or device mode if USB_VBUS is high.
- qcom,usbeth-reset-gpio: If present then an external usb-to-eth is connected to
the USB host controller and its RESET_N signal is connected to this
usbeth-reset-gpio GPIO. It should be driven LOW to RESET the usb-to-eth.
Example HSUSB OTG controller device node :
usb@f9690000 {
compatible = "qcom,hsusb-otg";
reg = <0xf9690000 0x400>;
reg-names = "core";
interrupts = <134>;
interrupt-names = "core_irq";
qcom,hsusb-otg-phy-type = <2>;
qcom,hsusb-otg-mode = <1>;
qcom,hsusb-otg-otg-control = <1>;
qcom,hsusb-otg-disable-reset;
qcom,hsusb-otg-pnoc-errata-fix;
qcom,hsusb-otg-default-mode = <2>;
qcom,hsusb-otg-phy-init-seq = <0x01 0x90 0xffffffff>;
qcom,hsusb-otg-power-budget = <500>;
qcom,hsusb-otg-pclk-src-name = "dfab_usb_clk";
qcom,hsusb-otg-lpm-on-dev-suspend;
qcom,hsusb-otg-clk-always-on-workaround;
hsusb_vdd_dig-supply = <&pm8226_s1_corner>;
HSUSB_1p8-supply = <&pm8226_l10>;
HSUSB_3p3-supply = <&pm8226_l20>;
qcom,vdd-voltage-level = <1 5 7>;
qcom,dp-manual-pullup;
qcom,hsusb-otg-mpm-dpsehv-int = <49>;
qcom,hsusb-otg-mpm-dmsehv-int = <58>;
qcom,max-nominal-sysclk-rate = <133330000>;
qcom,max-svs-sysclk-rate = <100000000>;
qcom,pm-qos-latency = <59>;
qcom,msm-bus,name = "usb2";
qcom,msm-bus,num_cases = <2>;
qcom,msm-bus,num_paths = <1>;
qcom,msm-bus,vectors =
<87 512 0 0>,
<87 512 60000000 960000000>;
pinctrl-names = "hsusb_active","hsusb_sleep";
pinctrl-0 = <&vddmin_act>;
pinctrl-0 = <&vddmin_sus>;
qcom,hsusb-otg-vddmin-gpio = <&pm8019_mpps 6 0>;
qcom,disable-retention-with-vdd-min;
qcom,usbin-vadc = <&pm8226_vadc>;
qcom,usbid-gpio = <&msm_gpio 110 0>;
};

2
arch/arm64/boot/dts/qcom/Makefile
View File

@ -318,6 +318,8 @@ dtb-$(CONFIG_ARCH_SDXPRAIRIE) += sdxprairie-rumi.dtb \
sa515m-v2-ccard-pcie-ep.dtb \
sa515m-v2-ccard-usb-ep.dtb
dtb-$(CONFIG_ARCH_MDM9607) += mdm9607-mtp.dtb
ifeq ($(CONFIG_ARM64),y)
always := $(dtb-y)
subdir-y := $(dts-dirs)

678
arch/arm64/boot/dts/qcom/mdm9607-bus.dtsi Normal file
View File

@ -0,0 +1,678 @@
/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/msm/msm-bus-ids.h>
&soc {
/* Version = 1 */
ad_hoc_bus: ad-hoc-bus {
compatible = "qcom,msm-bus-device";
reg = <0x401000 0x58000>,
<0x500000 0x15080>;
reg-names = "bimc-base", "pcnoc-base";
/*Buses*/
fab_bimc: fab-bimc {
cell-id = <MSM_BUS_FAB_BIMC>;
label = "fab-bimc";
qcom,fab-dev;
qcom,base-name = "bimc-base";
qcom,bus-type = <2>;
qcom,util-fact = <154>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&clock_gcc clk_bimc_msmbus_clk>,
<&clock_gcc clk_bimc_msmbus_a_clk>;
coresight-id = <203>;
coresight-name = "coresight-bimc";
coresight-nr-inports = <0>;
coresight-outports = <0>;
coresight-child-list = <&funnel_in0>;
coresight-child-ports = <3>;
};
fab_pcnoc: fab-pcnoc {
cell-id = <MSM_BUS_FAB_PERIPH_NOC>;
label = "fab-pcnoc";
qcom,fab-dev;
qcom,base-name = "pcnoc-base";
qcom,base-offset = <0x7000>;
qcom,qos-off = <0x1000>;
qcom,bus-type = <1>;
clock-names = "bus_clk", "bus_a_clk";
clocks = <&clock_gcc clk_pcnoc_msmbus_clk>,
<&clock_gcc clk_pcnoc_msmbus_a_clk>;
coresight-id = <201>;
coresight-name = "coresight-pcnoc";
coresight-nr-inports = <0>;
coresight-outports = <0>;
coresight-child-list = <&funnel_in2>;
coresight-child-ports = <0>;
};
/*Masters*/
mas_apps_proc: mas-apps-proc {
cell-id = <MSM_BUS_MASTER_AMPSS_M0>;
label = "mas-apps-proc";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,ap-owned;
qcom,qport = <0>;
qcom,qos-mode = "fixed";
qcom,connections = < &slv_bimc_pcnoc &slv_ebi>;
qcom,prio-lvl = <0>;
qcom,prio-rd = <0>;
qcom,prio-wr = <0>;
qcom,bus-dev = <&fab_bimc>;
qcom,mas-rpm-id = <ICBID_MASTER_APPSS_PROC>;
};
mas_pcnoc_bimc_1: mas-pcnoc-bimc-1 {
cell-id = <MSM_BUS_MASTER_PCNOC_BIMC_1>;
label = "mas-pcnoc-bimc-1";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,connections = <&slv_ebi>;
qcom,bus-dev = <&fab_bimc>;
qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_BIMC_1>;
};
mas_tcu_0: mas-tcu-0 {
cell-id = <MSM_BUS_MASTER_TCU_0>;
label = "mas-tcu-0";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,ap-owned;
qcom,qport = <5>;
qcom,qos-mode = "fixed";
qcom,connections = <&slv_ebi>;
qcom,prio-lvl = <2>;
qcom,prio-rd = <2>;
qcom,prio-wr = <2>;
qcom,bus-dev = <&fab_bimc>;
qcom,mas-rpm-id = <ICBID_MASTER_TCU_0>;
};
mas_qdss_bam: mas-qdss-bam {
cell-id = <MSM_BUS_MASTER_QDSS_BAM>;
label = "mas-qdss-bam";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,connections = <&qdss_int>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAM>;
qcom,blacklist = <&pcnoc_s_1 &pcnoc_s_2 &pcnoc_s_0
&pcnoc_s_4 &pcnoc_s_5 &pcnoc_s_3 &slv_tcu>;
};
mas_bimc_pcnoc: mas-bimc-pcnoc {
cell-id = <MSM_BUS_MASTER_BIMC_PCNOC>;
label = "mas-bimc-pcnoc";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,connections = <&pcnoc_int_0
&pcnoc_int_2 &slv_cats_0>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_BIMC_PCNOC>;
};
mas_qdss_etr: mas-qdss-etr {
cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
label = "mas-qdss-etr";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,connections = <&qdss_int>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>;
qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2
&pcnoc_s_3 &pcnoc_s_4 &pcnoc_s_5
&slv_crypto_0_cfg &slv_message_ram
&slv_pdm &slv_prng &slv_qdss_stm
&slv_tcu>;
};
mas_audio: mas-audio {
cell-id = <MSM_BUS_MASTER_AUDIO>;
label = "mas-audio";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,connections = <&pcnoc_m_0>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_AUDIO>;
qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_1
&pcnoc_s_2 &pcnoc_s_3
&pcnoc_s_4 &pcnoc_s_5 &slv_tcu>;
};
mas_qpic: mas-qpic {
cell-id = <MSM_BUS_MASTER_QPIC>;
label = "mas-qpic";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,connections = <&pcnoc_m_0>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_QPIC>;
qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2
&pcnoc_s_3 &pcnoc_s_4
&pcnoc_s_5 &slv_tcu
&slv_crypto_0_cfg &slv_pdm
&slv_prng &slv_usb2 >;
};
mas_hsic: mas-hsic {
cell-id = <MSM_BUS_MASTER_USB_HSIC>;
label = "mas-hsic";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,connections = <&pcnoc_m_0>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_USB_HSIC>;
};
mas_blsp_1: mas-blsp-1 {
cell-id = <MSM_BUS_MASTER_BLSP_1>;
label = "mas-blsp-1";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,connections = <&pcnoc_m_1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_BLSP_1>;
qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_1
&pcnoc_s_2 &pcnoc_s_3
&pcnoc_s_4 &pcnoc_s_5 &slv_tcu >;
};
mas_usb_hs1: mas-usb-hs1 {
cell-id = <MSM_BUS_MASTER_USB_HS>;
label = "mas-usb-hs1";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,connections = <&pcnoc_m_1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_USB_HS1>;
qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_4
&pcnoc_s_5 &slv_tcu
&slv_crypto_0_cfg
&slv_pdm &slv_prng &slv_usb2
&slv_usb_phy> ;
};
mas_crypto: mas-crypto {
cell-id = <MSM_BUS_MASTER_CRYPTO>;
label = "mas-crypto";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,ap-owned;
qcom,qport = <0>;
qcom,qos-mode = "fixed";
qcom,connections = <&pcnoc_int_3>;
qcom,prio1 = <2>;
qcom,prio0 = <2>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO>;
qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_3
&pcnoc_s_4 &pcnoc_s_5 &slv_tcu
&slv_crypto_0_cfg &slv_pdm
&slv_usb2 &slv_prng>;
};
mas_sdcc_1: mas-sdcc-1 {
cell-id = <MSM_BUS_MASTER_SDCC_1>;
label = "mas-sdcc-1";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,connections = <&pcnoc_int_3>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_SDCC_1>;
qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_3
&pcnoc_s_4 &pcnoc_s_5 &slv_tcu
&slv_crypto_0_cfg &slv_pdm
&slv_usb2 &slv_prng>;
};
mas_sdcc_2: mas-sdcc-2 {
cell-id = <MSM_BUS_MASTER_SDCC_2>;
label = "mas-sdcc-2";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,connections = <&pcnoc_int_3>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_SDCC_2>;
qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_3
&pcnoc_s_4 &pcnoc_s_5 &slv_tcu
&slv_crypto_0_cfg &slv_pdm
&slv_usb2 &slv_prng>;
};
mas_xi_usb_hs1: mas-xi-usb-hs1 {
cell-id = <MSM_BUS_MASTER_XM_USB_HS1>;
label = "mas-xi-usb-hs1";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_XI_USB_HS1>;
qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_4
&pcnoc_s_5 &slv_tcu &slv_crypto_0_cfg
&slv_pdm &slv_usb2 &slv_prng
&slv_usb_phy>;
};
mas_xi_hsic: mas-xi-hsic {
cell-id = <MSM_BUS_MASTER_XI_USB_HSIC>;
label = "mas-xi-hsic";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_XI_HSIC>;
qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2
&pcnoc_s_3 &pcnoc_s_4 &pcnoc_s_5
&slv_tcu &slv_crypto_0_cfg
&slv_pdm &slv_usb2 &slv_prng>;
};
mas_sgmii: mas-sgmii {
cell-id = <MSM_BUS_MASTER_SGMII>;
label = "mas-sgmii";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,ap-owned;
qcom,qport = <10>;
qcom,qos-mode = "fixed";
qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>;
qcom,prio1 = <1>;
qcom,prio0 = <1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_SGMII>;
qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_2 &pcnoc_s_3
&pcnoc_s_4 &pcnoc_s_5 &slv_tcu
&slv_crypto_0_cfg &slv_pdm
&slv_usb2 &slv_prng>;
};
/*Internal nodes*/
pcnoc_m_0: pcnoc-m-0 {
cell-id = <MSM_BUS_PNOC_M_0>;
label = "pcnoc-m-0";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_0>;
qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_0>;
};
pcnoc_m_1: pcnoc-m-1 {
cell-id = <MSM_BUS_PNOC_M_1>;
label = "pcnoc-m-1";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_1>;
qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_1>;
};
qdss_int: qdss-int {
cell-id = <MSM_BUS_SNOC_QDSS_INT>;
label = "qdss-int";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,connections = <&pcnoc_int_0 &slv_pcnoc_bimc_1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_QDSS_INT>;
qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_INT>;
};
pcnoc_int_0: pcnoc-int-0 {
cell-id = <MSM_BUS_PNOC_INT_0>;
label = "pcnoc-int-0";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,ap-owned;
qcom,connections = <&slv_imem &slv_qdss_stm>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_0>;
qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_0>;
};
pcnoc_int_2: pcnoc-int-2 {
cell-id = <MSM_BUS_PNOC_INT_2>;
label = "pcnoc-int-2";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,connections = <&pcnoc_s_1 &pcnoc_s_2
&pcnoc_s_0 &pcnoc_s_4
&pcnoc_s_5 &pcnoc_s_3
&slv_tcu >;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_2>;
qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_2>;
};
pcnoc_int_3: pcnoc-int-3 {
cell-id = <MSM_BUS_PNOC_INT_3>;
label = "pcnoc-int-3";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,connections = <&slv_pcnoc_bimc_1 &pcnoc_int_2>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_3>;
qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_3>;
};
pcnoc_s_0: pcnoc-s-0 {
cell-id = <MSM_BUS_PNOC_SLV_0>;
label = "pcnoc-s-0";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,connections = <&slv_tcsr &slv_sdcc_1 &slv_blsp_1
&slv_sgmii>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_0>;
qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_0>;
};
pcnoc_s_1: pcnoc-s-1 {
cell-id = <MSM_BUS_PNOC_SLV_1>;
label = "pcnoc-s-1";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,connections = <&slv_usb2 &slv_crypto_0_cfg
&slv_prng &slv_pdm
&slv_message_ram>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_1>;
qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_1>;
};
pcnoc_s_2: pcnoc-s-2 {
cell-id = <MSM_BUS_PNOC_SLV_2>;
label = "pcnoc-s-2";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,connections = <&slv_hsic &slv_sdcc_2 &slv_audio>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_2>;
qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_2>;
};
pcnoc_s_3: pcnoc-s-3 {
cell-id = <MSM_BUS_PNOC_SLV_3>;
label = "pcnoc-s-3";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,ap-owned;
qcom,connections = <&slv_usb_phy>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_3>;
qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_3>;
};
pcnoc_s_4: pcnoc-s-4 {
cell-id = <MSM_BUS_PNOC_SLV_4>;
label = "pcnoc-s-4";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,connections = <&slv_imem_cfg &slv_pmic_arb>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_4>;
qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_4>;
};
pcnoc_s_5: pcnoc-s-5 {
cell-id = <MSM_BUS_PNOC_SLV_5>;
label = "pcnoc-s-5";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,connections = <&slv_tlmm>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_5>;
qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_5>;
};
/*Slaves*/
slv_ebi:slv-ebi {
cell-id = <MSM_BUS_SLAVE_EBI_CH0>;
label = "slv-ebi";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_bimc>;
qcom,slv-rpm-id = <ICBID_SLAVE_EBI1>;
};
slv_bimc_pcnoc:slv-bimc-pcnoc {
cell-id = <MSM_BUS_SLAVE_BIMC_PCNOC>;
label = "slv-bimc-pcnoc";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_bimc>;
qcom,connections = <&mas_bimc_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_PCNOC>;
};
slv_pcnoc_bimc_1:slv-pcnoc-bimc-1 {
cell-id = <MSM_BUS_SLAVE_PCNOC_BIMC_1>;
label = "slv-pcnoc-bimc-1";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,connections = <&mas_pcnoc_bimc_1>;
qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_BIMC_1>;
};
slv_qdss_stm:slv-qdss-stm {
cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
label = "slv-qdss-stm";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,ap-owned;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>;
};
slv_cats_0:slv-cats-0 {
cell-id = <MSM_BUS_SLAVE_CATS_128>;
label = "slv-cats-0";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,ap-owned;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_CATS_0>;
};
slv_imem:slv-imem {
cell-id = <MSM_BUS_SLAVE_SYSTEM_IMEM>;
label = "slv-imem";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,ap-owned;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_IMEM>;
};
slv_tcsr:slv-tcsr {
cell-id = <MSM_BUS_SLAVE_TCSR>;
label = "slv-tcsr";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>;
};
slv_sdcc_1:slv-sdcc-1 {
cell-id = <MSM_BUS_SLAVE_SDCC_1>;
label = "slv-sdcc-1";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_1>;
};
slv_blsp_1:slv-blsp-1 {
cell-id = <MSM_BUS_SLAVE_BLSP_1>;
label = "slv-blsp-1";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_1>;
};
slv_sgmii:slv-sgmii {
cell-id = <MSM_BUS_SLAVE_SGMII>;
label = "slv-sgmii";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,ap-owned;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_SGMII>;
};
slv_crypto_0_cfg:slv-crypto-0-cfg {
cell-id = <MSM_BUS_SLAVE_CRYPTO_0_CFG>;
label = "slv-crypto-0-cfg";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,ap-owned;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_CRYPTO_0_CFG>;
};
slv_message_ram:slv-message-ram {
cell-id = <MSM_BUS_SLAVE_MESSAGE_RAM>;
label = "slv-message-ram";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_MESSAGE_RAM>;
};
slv_pdm:slv-pdm {
cell-id = <MSM_BUS_SLAVE_PDM>;
label = "slv-pdm";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_PDM>;
};
slv_prng:slv-prng {
cell-id = <MSM_BUS_SLAVE_PRNG>;
label = "slv-prng";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>;
};
slv_usb2:slv-usb2 {
cell-id = <MSM_BUS_SLAVE_USB_HS>;
label = "slv-usb2";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,ap-owned;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_USB_HS>;
};
slv_sdcc_2:slv-sdcc-2 {
cell-id = <MSM_BUS_SLAVE_SDCC_2>;
label = "slv-sdcc-2";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_2>;
};
slv_audio:slv-audio {
cell-id = <MSM_BUS_SLAVE_AUDIO>;
label = "slv-audio";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_AUDIO>;
};
slv_hsic:slv-hsic {
cell-id = <MSM_BUS_SLAVE_USB_HSIC>;
label = "slv-hsic";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_USB_HSIC>;
};
slv_usb_phy:slv-usb-phy {
cell-id = <MSM_BUS_SLAVE_USB_PHYS_CFG>;
label = "slv-usb-phy";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,ap-owned;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_USB_PHY_CFG>;
};
slv_tlmm:slv-tlmm {
cell-id = <MSM_BUS_SLAVE_TLMM>;
label = "slv-tlmm";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_TLMM>;
};
slv_imem_cfg:slv-imem-cfg {
cell-id = <MSM_BUS_SLAVE_IMEM_CFG>;
label = "slv-imem-cfg";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,ap-owned;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_IMEM_CFG>;
};
slv_pmic_arb:slv-pmic-arb {
cell-id = <MSM_BUS_SLAVE_PMIC_ARB>;
label = "slv-pmic-arb";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_PMIC_ARB>;
};
slv_tcu:slv-tcu {
cell-id = <MSM_BUS_SLAVE_TCU>;
label = "slv-tcu";
qcom,buswidth = <8>;
qcom,agg-ports = <1>;
qcom,ap-owned;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_TCU>;
};
slv_qipc {
cell-id = <MSM_BUS_SLAVE_QPIC>;
label = "slv-qpic";
qcom,buswidth = <4>;
qcom,agg-ports = <1>;
qcom,bus-dev = <&fab_pcnoc>;
qcom,slv-rpm-id = <ICBID_SLAVE_QPIC>;
};
};
};

462
arch/arm64/boot/dts/qcom/mdm9607-coresight.dtsi Normal file
View File

@ -0,0 +1,462 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&soc {
tmc_etr: tmc@6026000 {
compatible = "arm,coresight-tmc";
reg = <0x6026000 0x1000>,
<0x6084000 0x15000>;
reg-names = "tmc-base", "bam-base";
interrupts = <0 166 0>;
interrupt-names = "byte-cntr-irq";
qcom,memory-size = <0x100000>;
qcom,sg-enable;
coresight-id = <0>;
coresight-name = "coresight-tmc-etr";
coresight-nr-inports = <1>;
coresight-ctis = <&cti0 &cti8>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
tpiu: tpiu@6020000 {
compatible = "arm,coresight-tpiu";
reg = <0x6020000 0x1000>,
<0x1100000 0xb0000>;
reg-names = "tpiu-base", "nidnt-base";
coresight-id = <1>;
coresight-name = "coresight-tpiu";
coresight-nr-inports = <1>;
pinctrl-names = "sdcard", "trace", "swduart",
"swdtrc", "jtag", "spmi";
/* NIDnT */
pinctrl-0 = <&qdsd_clk_sdcard &qdsd_cmd_sdcard
&qdsd_data0_sdcard &qdsd_data1_sdcard
&qdsd_data2_sdcard &qdsd_data3_sdcard>;
pinctrl-1 = <&qdsd_clk_trace &qdsd_cmd_trace
&qdsd_data0_trace &qdsd_data1_trace
&qdsd_data2_trace &qdsd_data3_trace>;
pinctrl-2 = <&qdsd_cmd_swduart &qdsd_data0_swduart
&qdsd_data1_swduart &qdsd_data2_swduart
&qdsd_data3_swduart>;
pinctrl-3 = <&qdsd_clk_swdtrc &qdsd_cmd_swdtrc
&qdsd_data0_swdtrc &qdsd_data1_swdtrc
&qdsd_data2_swdtrc &qdsd_data3_swdtrc>;
pinctrl-4 = <&qdsd_cmd_jtag &qdsd_data0_jtag
&qdsd_data1_jtag &qdsd_data2_jtag
&qdsd_data3_jtag>;
pinctrl-5 = <&qdsd_clk_spmi &qdsd_cmd_spmi
&qdsd_data0_spmi &qdsd_data3_spmi>;
qcom,nidnthw;
qcom,nidnt-swduart;
qcom,nidnt-swdtrc;
qcom,nidnt-jtag;
qcom,nidnt-spmi;
nidnt-gpio = <26>;
nidnt-gpio-polarity = <1>;
interrupts = <0 82 0>;
interrupt-names = "nidnt-irq";
vdd-supply = <&sdcard_ext_vreg>;
qcom,vdd-voltage-level = <2850000 2850000>;
qcom,vdd-current-level = <15 400000>;
vdd-io-supply = <&mdm9607_l13>;
qcom,vdd-io-voltage-level = <1800000 2950000>;
qcom,vdd-io-current-level = <200 300000>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
replicator: replicator@6024000 {
compatible = "qcom,coresight-replicator";
reg = <0x6024000 0x1000>;
reg-names = "replicator-base";
coresight-id = <2>;
coresight-name = "coresight-replicator";
coresight-nr-inports = <1>;
coresight-outports = <0 1>;
coresight-child-list = <&tmc_etr &tpiu>;
coresight-child-ports = <0 0>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
tmc_etf: tmc@6025000 {
compatible = "arm,coresight-tmc";
reg = <0x6025000 0x1000>;
reg-names = "tmc-base";
coresight-id = <3>;
coresight-name = "coresight-tmc-etf";
coresight-nr-inports = <1>;
coresight-outports = <0>;
coresight-child-list = <&replicator>;
coresight-child-ports = <0>;
coresight-default-sink;
coresight-ctis = <&cti0 &cti8>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
funnel_in0: funnel@6021000 {
compatible = "arm,coresight-funnel";
reg = <0x6021000 0x1000>;
reg-names = "funnel-base";
coresight-id = <4>;
coresight-name = "coresight-funnel-in0";
coresight-nr-inports = <8>;
coresight-outports = <0>;
coresight-child-list = <&tmc_etf>;
coresight-child-ports = <0>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
funnel_in2: funnel@6068000 {
compatible = "arm,coresight-funnel";
reg = <0x6068000 0x1000>;
reg-names = "funnel-base";
coresight-id = <5>;
coresight-name = "coresight-funnel-in2";
coresight-nr-inports = <2>;
coresight-outports = <0>;
coresight-child-list = <&funnel_in0>;
coresight-child-ports = <6>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
cti0: cti@6010000 {
compatible = "arm,coresight-cti";
reg = <0x6010000 0x1000>;
reg-names = "cti-base";
coresight-id = <6>;
coresight-name = "coresight-cti0";
coresight-nr-inports = <0>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
cti1: cti@6011000 {
compatible = "arm,coresight-cti";
reg = <0x6011000 0x1000>;
reg-names = "cti-base";
coresight-id = <7>;
coresight-name = "coresight-cti1";
coresight-nr-inports = <0>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
cti2: cti@6012000 {
compatible = "arm,coresight-cti";
reg = <0x6012000 0x1000>;
reg-names = "cti-base";
coresight-id = <8>;
coresight-name = "coresight-cti2";
coresight-nr-inports = <0>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
cti3: cti@6013000 {
compatible = "arm,coresight-cti";
reg = <0x6013000 0x1000>;
reg-names = "cti-base";
coresight-id = <9>;
coresight-name = "coresight-cti3";
coresight-nr-inports = <0>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
cti4: cti@6014000 {
compatible = "arm,coresight-cti";
reg = <0x6014000 0x1000>;
reg-names = "cti-base";
coresight-id = <10>;
coresight-name = "coresight-cti4";
coresight-nr-inports = <0>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
cti5: cti@6015000 {
compatible = "arm,coresight-cti";
reg = <0x6015000 0x1000>;
reg-names = "cti-base";
coresight-id = <11>;
coresight-name = "coresight-cti5";
coresight-nr-inports = <0>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
cti6: cti@6016000 {
compatible = "arm,coresight-cti";
reg = <0x6016000 0x1000>;
reg-names = "cti-base";
coresight-id = <12>;
coresight-name = "coresight-cti6";
coresight-nr-inports = <0>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
cti7: cti@6017000 {
compatible = "arm,coresight-cti";
reg = <0x6017000 0x1000>;
reg-names = "cti-base";
coresight-id = <13>;
coresight-name = "coresight-cti7";
coresight-nr-inports = <0>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
cti8: cti@6018000 {
compatible = "arm,coresight-cti";
reg = <0x6018000 0x1000>;
reg-names = "cti-base";
coresight-id = <14>;
coresight-name = "coresight-cti8";
coresight-nr-inports = <0>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
cti_cpu0: cti@6043000 {
compatible = "arm,coresight-cti";
reg = <0x6043000 0x1000>;
reg-names = "cti-base";
coresight-id = <15>;
coresight-name = "coresight-cti-cpu0";
coresight-nr-inports = <0>;
coresight-cti-cpu = <&CPU0>;
qcom,cti-save;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
cti_rpm_cpu0: cti@603c000 {
compatible = "arm,coresight-cti";
reg = <0x603c000 0x1000>;
reg-names = "cti-base";
coresight-id = <16>;
coresight-name = "coresight-cti-rpm-cpu0";
coresight-nr-inports = <0>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
cti_modem_cpu0: cti@6038000 {
compatible = "arm,coresight-cti";
reg = <0x6038000 0x1000>;
reg-names = "cti-base";
coresight-id = <17>;
coresight-name = "coresight-cti-modem-cpu0";
coresight-nr-inports = <0>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
stm: stm@6002000 {
compatible = "arm,coresight-stm";
reg = <0x6002000 0x1000>,
<0x9280000 0x180000>;
reg-names = "stm-base", "stm-data-base";
coresight-id = <18>;
coresight-name = "coresight-stm";
coresight-nr-inports = <0>;
coresight-outports = <0>;
coresight-child-list = <&funnel_in0>;
coresight-child-ports = <7>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
csr: csr@6001000 {
compatible = "qcom,coresight-csr";
reg = <0x6001000 0x1000>;
reg-names = "csr-base";
coresight-id = <19>;
coresight-name = "coresight-csr";
coresight-nr-inports = <0>;
qcom,blk-size = <1>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
etm0: etm@6042000 {
compatible = "arm,coresight-etm";
reg = <0x6042000 0x1000>;
reg-names = "etm-base";
coresight-id = <20>;
coresight-name = "coresight-etm0";
coresight-nr-inports = <0>;
coresight-outports = <0>;
coresight-child-list = <&funnel_in0>;
coresight-child-ports = <4>;
coresight-etm-cpu = <&CPU0>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
hwevent: hwevent@606c000 {
compatible = "qcom,coresight-hwevent";
reg = <0x606c000 0x148>,
<0x606cfb0 0x4>,
<0x78640cc 0x4>,
<0x78240cc 0x4>,
<0x7885010 0x4>,
<0x200c004 0x4>,
<0x78d90a0 0x4>;
reg-names = "wrapper-mux", "wrapper-lockaccess",
"wrapper-sdcc2", "wrapper-sdcc1",
"blsp-mux", "spmi-mux" ,"usb-mux";
coresight-id = <21>;
coresight-name = "coresight-hwevent";
coresight-nr-inports = <0>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
rpm_etm0 {
compatible = "qcom,coresight-remote-etm";
coresight-id = <22>;
coresight-name = "coresight-rpm-etm0";
coresight-nr-inports = <0>;
coresight-outports = <0>;
coresight-child-list = <&funnel_in0>;
coresight-child-ports = <0>;
qcom,inst-id = <4>;
};
modem_etm0 {
compatible = "qcom,coresight-remote-etm";
coresight-id = <23>;
coresight-name = "coresight-modem-etm0";
coresight-nr-inports = <0>;
coresight-outports = <0>;
coresight-child-list = <&funnel_in0>;
coresight-child-ports = <2>;
qcom,inst-id = <2>;
};
fuse: fuse@a601c {
compatible = "arm,coresight-fuse-v2";
reg = <0xa601c 0x8>;
reg-names = "fuse-base";
coresight-id = <24>;
coresight-name = "coresight-fuse";
coresight-nr-inports = <0>;
};
dbgui: dbgui@606d000 {
compatible = "qcom,coresight-dbgui";
reg = <0x606d000 0x1000>;
reg-names = "dbgui-base";
coresight-id = <25>;
coresight-name = "coresight-dbgui";
coresight-nr-inports = <0>;
coresight-outports = <0>;
coresight-child-list = <&funnel_in2>;
coresight-child-ports = <1>;
qcom,dbgui-addr-offset = <0x30>;
qcom,dbgui-data-offset = <0xB0>;
qcom,dbgui-size = <32>;
clocks = <&clock_gcc clk_qdss_clk>,
<&clock_gcc clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
};
};

36
arch/arm64/boot/dts/qcom/mdm9607-display.dtsi Normal file
View File

@ -0,0 +1,36 @@
/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/ {
mdss_qpic: qcom,msm_qpic@7980000 {
compatible = "qcom,mdss_qpic";
reg = <0x7980000 0x24000>;
reg-names = "qpic_base";
interrupts = <0 251 0>;
qcom,msm-bus,name = "mdss_qpic";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<91 512 0 0>,
/* Voting for max b/w on PNOC bus for now */
<91 512 400000 800000>;
vdd-supply = <&mdm9607_l11>;
clock-names = "core_clk", "core_a_clk";
clocks = <&clock_gcc clk_qpic_clk>,
<&clock_gcc clk_qpic_a_clk>;
};
};

37
arch/arm64/boot/dts/qcom/mdm9607-ion.dtsi Normal file
View File

@ -0,0 +1,37 @@
/*
* Copyright (c) 2015,2017, Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&soc {
qcom,ion {
compatible = "qcom,msm-ion";
#address-cells = <1>;
#size-cells = <0>;
qcom,ion-heap@25 {
reg = <25>;
qcom,ion-heap-type = "SYSTEM";
};
qcom,ion-heap@28 { /* AUDIO HEAP */
reg = <28>;
memory-region = <&audio_mem>;
qcom,ion-heap-type = "DMA";
};
qcom,ion-heap@27 { /* QSEECOM HEAP */
reg = <27>;
memory-region = <&qseecom_mem>;
qcom,ion-heap-type = "DMA";
};
};
};

22
arch/arm64/boot/dts/qcom/mdm9607-mtp.dts Normal file
View File

@ -0,0 +1,22 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "mdm9607-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MDM 9607 MTP";
compatible = "qcom,mdm9607-mtp", "qcom,mdm9607", "qcom,mtp";
qcom,board-id = <8 0>;
};

209
arch/arm64/boot/dts/qcom/mdm9607-mtp.dtsi Normal file
View File

@ -0,0 +1,209 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "mdm9607.dtsi"
#include "mdm9607-pinctrl.dtsi"
#include "mdm9607-display.dtsi"
#include "qpic-panel-ili-hvga.dtsi"
/ {
bluetooth: bt_qca6174 {
compatible = "qca,qca6174";
qca,bt-reset-gpio = <&pm8019_gpios 2 0>; /* BT_EN */
qca,bt-vdd-pa-supply = <&rome_vreg>;
qca,bt-vdd-io-supply = <&mdm9607_l11>;
qca,bt-vdd-xtal-supply = <&mdm9607_l2>;
qca,bt-vdd-io-voltage-level = <1800000 1800000>;
qca,bt-vdd-xtal-voltage-level = <1800000 1800000>;
};
};
&soc {
};
&blsp1_uart5 {
status = "ok";
pinctrl-names = "default";
pinctrl-0 = <&uart_console_sleep>;
};
&i2c_4 {
status = "ok";
};
&spi_1 {
status = "ok";
can-controller@0 {
compatible = "fsl,k61";
spi-max-frequency = <4800000>;
reg = <0>;
interrupt-parent = <&tlmm_pinmux>;
interrupts = <25 0>;
reset-gpio = <&tlmm_pinmux 11 0x1>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&can_rst_on>;
pinctrl-1 = <&can_rst_off>;
};
};
&blsp1_uart3 {
status = "ok";
};
&qnand_1 {
status = "ok";
};
&emac0 {
status = "ok";
};
/* MPP pin 2 configs for SMB358 interrupt line */
&pm8019_mpps {
mpp@a100 {
qcom,mode = <0>; /* Digital input */
qcom,vin-sel = <3>; /* 1.8V (L11) */
qcom,src-sel = <0>; /* QPNP_PIN_SEL_FUNC_CONSTANT */
qcom,pull = <2>; /* PULL UP 10KOHM */
qcom,master-en = <1>;
};
};
&pm8019_gpios {
gpio@c100 { /* BT_EN */
qcom,mode = <1>; /* Digital output*/
qcom,pull = <4>; /* Pulldown 10uA */
qcom,vin-sel = <2>; /* VIN2 */
qcom,src-sel = <0>; /* GPIO */
qcom,invert = <0>; /* Invert */
qcom,master-en = <1>; /* Enable GPIO */
status = "ok";
};
/* PMIC gpio for wlan power supply */
gpio@c200 {
qcom,mode = <1>; /* Digital output */
qcom,output-type = <0>; /* CMOS logic */
qcom,invert = <1>; /* Output high */
qcom,vin-sel = <3>; /* VPH_PWR */
qcom,src-sel = <0>; /* Constant */
qcom,out-strength = <1>; /* High drive strength */
qcom,master-en = <1>; /* Enable GPIO */
status = "okay";
};
/* ROME 32k Sleep Clock */
gpio@c500 {
qcom,mode = <1>; /* Digital output */
qcom,output-type = <0>; /* CMOS logic */
qcom,invert = <0>; /* no inversion */
qcom,vin-sel = <2>; /* VIN 2 */
qcom,src-sel = <2>; /* Function 2 */
qcom,out-strength = <2>; /* Medium */
qcom,master-en = <1>; /* Enable GPIO */
status = "ok";
};
};
&sdhc_1 {
vdd-io-supply = <&mdm9607_l11>;
qcom,vdd-io-always-on;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 30000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pmx_sdc1_clk_on &pmx_sdc1_cmd_on &pmx_sdc1_data_on
&sdc1_wlan_gpio_active>;
pinctrl-1 = <&pmx_sdc1_clk_off &pmx_sdc1_cmd_off &pmx_sdc1_data_off
&sdc1_wlan_gpio_sleep>;
qcom,nonremovable;
qcom,core_3_0v_support;
status = "ok";
};
&pm8019_gpios {
gpio@c300 { /* GPIO 4 */
qcom,mode = <1>; /* Digital output */
qcom,output-type = <0>; /* CMOS logic */
qcom,invert = <0>; /* Output high */
qcom,vin-sel = <0>; /* VPH_PWR */
qcom,src-sel = <0>; /* GPIO */
qcom,out-strength = <1>; /* Low drive strength */
qcom,master-en = <1>; /* Enable GPIO */
};
};
/* MPP pin 4 configs for SGMII */
&pm8019_mpps {
mpp@a300 { /* MPP 4 */
qcom,mode = <1>; /* Digital output */
qcom,vin-sel = <2>; /* 1.8V */
qcom,src-sel = <0>; /* Constant */
qcom,master-en = <1>; /* Enable GPIO */
status = "okay";
};
};
&i2c_4 {
/* SMB358 charger configuration */
smb358_otg_vreg: smb358-charger@57 {
compatible = "qcom,smb358-charger";
regulator-name = "smb358_otg_vreg";
reg = <0x57>;
interrupt-parent = <&spmi_bus>;
interrupts = <0x0 0xa1 0x0>; /* PMIC MPP 2 */
qcom,float-voltage-mv = <4200>;
qcom,irq-gpio = <&pm8019_mpps 2 0>;
qcom,chg-vadc = <&pm8019_vadc>;
qcom,batt-id-vref-uv = <1800000>;
qcom,batt-id-rpullup-kohm = <220>;
};
};
&sdhc_2 {
vdd-supply = <&sdcard_ext_vreg>;
qcom,vdd-voltage-level = <2850000 2850000>;
qcom,vdd-current-level = <15000 400000>;
vdd-io-supply = <&mdm9607_l13>;
qcom,vdd-io-voltage-level = <1800000 2850000>;
qcom,vdd-io-current-level = <200 50000>;
#address-cells = <0>;
interrupt-parent = <&sdhc_2>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 125 0
1 &intc 0 221 0
2 &tlmm_pinmux 26 0>;
interrupt-names = "hc_irq", "pwr_irq", "status_irq";
cd-gpios = <&tlmm_pinmux 26 0x1>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
status = "disabled";
};
/* Display */
&mdss_qpic {
pinctrl-names= "mdss_default", "mdss_sleep";
pinctrl-0 = <&mdss_ldo_active &mdss_cs_active &mdss_te_active
&mdss_rs_active &mdss_ad_active &mdss_bl_active>;
pinctrl-1 = <&mdss_ldo_sleep &mdss_cs_sleep &mdss_te_sleep
&mdss_rs_sleep &mdss_ad_sleep &mdss_bl_sleep>;
status = "disabled";
};

1106
arch/arm64/boot/dts/qcom/mdm9607-pinctrl.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

258
arch/arm64/boot/dts/qcom/mdm9607-pm.dtsi Normal file
View File

@ -0,0 +1,258 @@
/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/msm/pm.h>
&soc {
qcom,spm@b009000 {
compatible = "qcom,spm-v2";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb009000 0x1000>;
qcom,name = "cpu0";
qcom,cpu = <&CPU0>;
qcom,saw2-ver-reg = <0xfd0>;
qcom,saw2-cfg = <0x1>;
qcom,saw2-spm-dly= <0x3c102800>;
qcom,saw2-spm-ctl = <0xe>;
qcom,mode0 {
qcom,label = "qcom,saw2-spm-cmd-wfi";
qcom,sequence = [04 03 04 0f];
qcom,spm_en;
};
qcom,mode1 {
qcom,label = "qcom,saw2-spm-cmd-spc";
qcom,sequence = [1f 34 04 44 24 54 03
54 44 04 24 34 0f];
qcom,spm_en;
qcom,pc_mode;
};
qcom,mode2 {
qcom,label = "qcom,saw2-spm-cmd-pc";
qcom,sequence = [1f 34 04 44 14 24 54 03
54 44 14 04 04 24 04 34 0f];
qcom,spm_en;
qcom,pc_mode;
qcom,slp_cmd_mode;
};
};
qcom,lpm-levels {
compatible = "qcom,lpm-levels";
#address-cells = <1>;
#size-cells = <0>;
qcom,pm-cluster@0{
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
label = "system";
qcom,default-level=<0>;
qcom,pm-cluster-level@0 {
reg = <0>;
label = "l2-active";
qcom,latency-us = <270>;
qcom,ss-power = <455>;
qcom,energy-overhead = <270621>;
qcom,time-overhead = <500>;
};
qcom,pm-cluster-level@1 {
reg = <1>;
label = "l2-pc";
qcom,latency-us = <285>;
qcom,ss-power = <442>;
qcom,energy-overhead = <306621>;
qcom,time-overhead = <540>;
qcom,min-child-idx = <2>;
qcom,notify-rpm;
qcom,reset-level = <LPM_RESET_LVL_PC>;
};
qcom,pm-cpu {
#address-cells = <1>;
#size-cells = <0>;
qcom,pm-cpu-level@0{
reg = <0>;
qcom,spm-cpu-mode = "wfi";
qcom,latency-us = <1>;
qcom,ss-power = <473>;
qcom,energy-overhead = <100000>;
qcom,time-overhead = <25>;
};
qcom,pm-cpu-level@1 {
reg = <1>;
qcom,spm-cpu-mode ="standalone_pc";
qcom,latency-us = <240>;
qcom,ss-power = <467>;
qcom,energy-overhead = <202781>;
qcom,time-overhead = <420>;
qcom,use-broadcast-timer;
qcom,is-reset;
qcom,reset-level = <LPM_RESET_LVL_PC>;
};
qcom,pm-cpu-level@2 {
reg = <2>;
qcom,spm-cpu-mode = "pc";
qcom,latency-us = <270>;
qcom,ss-power = <455>;
qcom,energy-overhead = <270621>;
qcom,time-overhead = <500>;
qcom,use-broadcast-timer;
qcom,is-reset;
qcom,reset-level = <LPM_RESET_LVL_PC>;
};
};
};
};
qcom,mpm@601d0 {
compatible = "qcom,mpm-v2";
reg = <0x601d0 0x1000>, /* MSM_RPM_MPM_BASE 4K */
<0xb011008 0x4>;
reg-names = "vmpm", "ipc";
interrupts = <0 171 1>;
clocks = <&clock_gcc clk_xo_lpm_clk>;
clock-names = "xo";
qcom,ipc-bit-offset = <1>;
qcom,gic-parent = <&intc>;
qcom,gic-map = <2 216>, /* tsens_upper_lower_int */
<49 172>, /* usb1_hs_async_wakeup_irq */
<51 174>, /* usb2_hs_async_wakeup_irq */
<53 104>, /* mdss_irq */
<58 166>, /* usb_hs_irq */
<62 222>, /* ee0_apps_hlos_spmi_periph_irq */
<0xff 18>, /* WDT_biteInt */
<0xff 19>, /* WDT_barkInt */
<0xff 35>, /* CTI_SPI_intx */
<0xff 38>, /* QTMR_qgicFrm0VirtIrq */
<0xff 47>,
<0xff 56>, /* q6_wdog_expired_irq */
<0xff 57>, /* mss_to_apps_irq(0) */
<0xff 58>, /* mss_to_apps_irq(1) */
<0xff 59>, /* mss_to_apps_irq(2) */
<0xff 60>, /* mss_to_apps_irq(3) */
<0xff 61>, /* mss_a2_bam_irq */
<0xff 77>, /* qpic_bam_irq[1] */
<0xff 114>, /* qdsd_intr_out */
<0xff 130>, /* peripheral_irq[9] */
<0xff 131>, /* qup_irq */
<0xff 140>, /* uart_dm_intr */
<0xff 153>, /* peripheral_irq[4] */
<0xff 155>, /* sdc1_irq(0) */
<0xff 157>, /* sdc2_irq(0) */
<0xff 161>, /* qpic_nandc_op_done_irq */
<0xff 163>, /* qpic_lcdc_irq */
<0xff 164>, /* qpic_bam_irq[0] */
<0xff 168>,
<0xff 170>, /* sdc1_pwr_cmd_irq */
<0xff 173>, /* hsic_core_irq */
<0xff 192>, /* audio_out0_irq */
<0xff 198>, /* qdss_etrbytecnt_irq */
<0xff 200>, /* rpm_ipc(4) */
<0xff 201>, /* rpm_ipc(5) */
<0xff 202>, /* rpm_ipc(6) */
<0xff 203>, /* rpm_ipc(7) */
<0xff 204>, /* rpm_ipc(24) */
<0xff 205>, /* rpm_ipc(25) */
<0xff 206>, /* rpm_ipc(26) */
<0xff 207>, /* rpm_ipc(27) */
<0xff 208>, /* rbif_irq[0] */
<0xff 215>, /* o_bimc_intr */
<0xff 224>, /* spdm_realtime_irq(1) */
<0xff 239>, /* crypto_bam_irq[1]*/
<0xff 240>, /* summary_irq_kpss */
<0xff 244>, /* bam_irq[2] */
<0xff 253>, /* sdc2_pwr_cmd_irq */
<0xff 269>, /* rpm_wdog_expired_irq */
<0xff 270>, /* bam_irq[0] */
<0xff 275>, /* rpm_ipc(30) */
<0xff 276>; /* rpm_ipc(31) */
qcom,gpio-parent = <&tlmm_pinmux>;
qcom,gpio-map = <3 16>,
<4 5>,
<5 11>,
<6 12>,
<7 3>,
<8 17>,
<9 9>,
<10 13>,
<11 1>,
<12 20>,
<13 21>,
<14 22>,
<15 75>,
<16 74>,
<17 28>,
<18 44>,
<19 26>,
<20 43>,
<21 42>,
<22 29>,
<23 69>,
<24 30>,
<25 37>,
<26 25>,
<27 71>,
<28 34>,
<29 55>,
<30 8>,
<31 40>,
<32 48>,
<33 52>,
<34 57>,
<35 62>,
<36 66>,
<37 59>,
<38 79>,
<39 38>,
<40 63>,
<41 76>;
};
qcom,pm@8600664 {
compatible = "qcom,pm";
reg = <0x8600664 0x40>;
clocks = <&clock_cpu clk_a7ssmux>;
clock-names = "cpu0_clk";
qcom,use-sync-timer;
qcom,synced-clocks;
qcom,tz-flushes-cache;
};
qcom,cpu-sleep-status@b088008{
compatible = "qcom,cpu-sleep-status";
reg = <0xb088008 0x100>;
qcom,cpu-alias-addr = <0x10000>;
qcom,sleep-status-mask= <0x80000>;
};
qcom,rpm-stats@29dba0 {
compatible = "qcom,rpm-stats";
reg = <0x29dba0 0x1000>;
reg-names = "phys_addr_base";
qcom,sleep-stats-version = <2>;
};
qcom,rpm-master-stats@60150 {
compatible = "qcom,rpm-master-stats";
reg = <0x60150 0x2030>;
qcom,masters = "APSS", "MPSS", "PRONTO";
qcom,master-stats-version = <2>;
qcom,master-offset = <4096>;
};
};

413
arch/arm64/boot/dts/qcom/mdm9607-regulator.dtsi Normal file
View File

@ -0,0 +1,413 @@
/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&rpm_bus {
rpm-regulator-smpa2 {
status = "okay";
mdm9607_s2: regulator-s2 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_s2";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1275000>;
qcom,init-voltage = <750000>;
status = "okay";
};
};
/* CX supply */
rpm-regulator-smpa3 {
status = "okay";
mdm9607_s3_level: regulator-s3-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_s3_level";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_TURBO>;
qcom,use-voltage-level;
};
mdm9607_s3_level_ao: regulator-s3-level-ao {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_s3_level_ao";
qcom,set = <1>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_TURBO>;
qcom,use-voltage-level;
};
mdm9607_s3_floor_level: regulator-s3-floor-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_s3_floor_level";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_TURBO>;
qcom,use-voltage-floor-level;
qcom,always-send-voltage;
};
mdm9607_s3_level_so: regulator-s3-level-so {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_s3_level_so";
qcom,set = <2>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_TURBO>;
qcom,use-voltage-level;
};
};
rpm-regulator-smpa4 {
status = "okay";
mdm9607_s4: regulator-s4 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_s4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1950000>;
qcom,init-voltage = <1800000>;
status = "okay";
};
};
rpm-regulator-ldoa1 {
status = "okay";
mdm9607_l1: regulator-l1 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l1";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
qcom,init-voltage = <1250000>;
status = "okay";
};
};
rpm-regulator-ldoa2 {
status = "okay";
mdm9607_l2: regulator-l2 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,init-voltage = <1800000>;
status = "okay";
};
};
rpm-regulator-ldoa3 {
status = "okay";
mdm9607_l3: regulator-l3 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,init-voltage = <1800000>;
status = "okay";
};
};
rpm-regulator-ldoa4 {
status = "okay";
mdm9607_l4: regulator-l4 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l4";
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
qcom,init-voltage = <3075000>;
status = "okay";
};
};
rpm-regulator-ldoa5 {
status = "okay";
mdm9607_l5: regulator-l5 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l5";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3050000>;
qcom,init-voltage = <1700000>;
status = "okay";
};
};
rpm-regulator-ldoa6 {
status = "okay";
mdm9607_l6: regulator-l6 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l6";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <3050000>;
qcom,init-voltage = <1700000>;
status = "okay";
};
};
rpm-regulator-ldoa7 {
status = "okay";
mdm9607_l7: regulator-l7 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l7";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <1900000>;
qcom,init-voltage = <1700000>;
status = "okay";
};
};
rpm-regulator-ldoa8 {
status = "okay";
mdm9607_l8: regulator-l8 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,init-voltage = <1800000>;
status = "okay";
};
};
rpm-regulator-ldoa9 {
status = "okay";
mdm9607_l9: regulator-l9 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l9";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1250000>;
qcom,init-voltage = <1200000>;
status = "okay";
};
};
rpm-regulator-ldoa10 {
status = "okay";
mdm9607_l10: regulator-l10 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l10";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
qcom,init-voltage = <1050000>;
status = "okay";
};
};
rpm-regulator-ldoa11 {
status = "okay";
mdm9607_l11: regulator-l11 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l11";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,init-voltage = <1800000>;
status = "okay";
};
};
/* MX supply */
rpm-regulator-ldoa12 {
status = "okay";
mdm9607_l12_level: regulator-l12-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l12_level";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_TURBO>;
qcom,use-voltage-level;
};
mdm9607_l12_level_ao: regulator-l12-level-ao {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l12_level_ao";
qcom,set = <1>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_TURBO>;
qcom,use-voltage-level;
qcom,always-send-voltage;
};
mdm9607_l12_level_so: regulator-l12-level-so {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l12_level_so";
qcom,set = <2>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_TURBO>;
qcom,use-voltage-level;
};
mdm9607_l12_floor_level: regulator-l12-floor-level {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l12_floor_lebel";
qcom,set = <3>;
regulator-min-microvolt =
<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
regulator-max-microvolt =
<RPM_SMD_REGULATOR_LEVEL_TURBO>;
qcom,use-voltage-floor-level;
qcom,always-send-voltage;
};
};
rpm-regulator-ldoa13 {
status = "okay";
mdm9607_l13: regulator-l13 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l13";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2850000>;
qcom,init-voltage = <2850000>;
status = "okay";
};
};
rpm-regulator-ldoa14 {
status = "okay";
mdm9607_l14: regulator-l14 {
compatible = "qcom,rpm-smd-regulator";
regulator-name = "mdm9607_l14";
regulator-min-microvolt = <2650000>;
regulator-max-microvolt = <3000000>;
qcom,init-voltage = <2650000>;
status = "okay";
};
};
};
&spmi_bus {
qcom,pm8019@1 {
/* APC supply */
mdm9607_s1: spm-regulator@1400 {
compatible = "qcom,spm-regulator";
reg = <0x1400 0x100>;
regulator-name = "mdm9607_s1";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1350000>;
qcom,bypass-spm; /* TODO: Remove once SPM is up */
};
};
};
&soc {
mem_acc_vreg_corner: regulator@1942130 {
compatible = "qcom,mem-acc-regulator";
reg = <0x1942130 0x4>;
reg-names = "acc-sel-l1";
regulator-name = "mem_acc_corner";
regulator-min-microvolt = <1>;
regulator-max-microvolt = <3>;
qcom,acc-sel-l1-bit-pos = <0>;
qcom,corner-acc-map = <0 1 1>;
};
apc_vreg_corner: regulator@b018000 {
compatible = "qcom,cpr-regulator";
reg = <0xb018000 0x1000>, <0xb010058 4>, <0xa4000 0x1000>;
reg-names = "rbcpr", "rbcpr_clk", "efuse_addr";
interrupts = <0 20 0>;
regulator-name = "apc_corner";
qcom,cpr-fuse-corners = <3>;
regulator-min-microvolt = <1>;
regulator-max-microvolt = <7>;
qcom,cpr-voltage-ceiling = <1050000 1225000 1350000>;
qcom,cpr-voltage-floor = <1050000 1050000 1150000>;
vdd-apc-supply = <&mdm9607_s1>;
vdd-mx-supply = <&mdm9607_l12_level_ao>;
qcom,vdd-mx-vmin-method = <4>;
qcom,vdd-mx-corner-map = < RPM_SMD_REGULATOR_LEVEL_SVS
RPM_SMD_REGULATOR_LEVEL_NOM
RPM_SMD_REGULATOR_LEVEL_TURBO >;
qcom,vdd-mx-vmax = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
mem-acc-supply = <&mem_acc_vreg_corner>;
qcom,cpr-ref-clk = <19200>;
qcom,cpr-timer-delay = <5000>;
qcom,cpr-timer-cons-up = <0>;
qcom,cpr-timer-cons-down = <2>;
qcom,cpr-irq-line = <0>;
qcom,cpr-step-quotient = <22 0 24 0 0 0 0 0>;
qcom,cpr-up-threshold = <2>;
qcom,cpr-down-threshold = <3>;
qcom,cpr-idle-clocks = <15>;
qcom,cpr-gcnt-time = <1>;
qcom,vdd-apc-step-up-limit = <1>;
qcom,vdd-apc-step-down-limit = <1>;
qcom,cpr-apc-volt-step = <12500>;
qcom,cpr-fuse-row = <65 0>;
qcom,cpr-fuse-target-quot = <24 12 0>;
qcom,cpr-fuse-ro-sel = <42 39 36>;
qcom,cpr-fuse-bp-cpr-disable = <54>;
qcom,cpr-fuse-init-voltage =
<66 6 6 0>,
<66 0 6 0>,
<65 45 6 0>;
qcom,cpr-fuse-revision = <65 51 3 0>;
qcom,cpr-init-voltage-ref = <1050000 1225000 1350000>;
qcom,cpr-init-voltage-step = <10000>;
qcom,cpr-corner-map = <1 2 3 3 3 3 3>;
qcom,cpr-init-voltage-as-ceiling;
qcom,cpr-corner-frequency-map =
<1 400000000>,
<2 800000000>,
<3 998400000>,
<4 1094400000>,
<5 1190400000>,
<6 1248000000>,
<7 1305600000>;
qcom,speed-bin-fuse-sel = <37 34 3 0>;
qcom,cpr-speed-bin-max-corners =
<0 0 1 2 7>;
qcom,cpr-quot-adjust-scaling-factor-max = <1400>;
qcom,disable-closed-loop-in-pc;
qcom,cpr-cpus = <&CPU0>;
qcom,cpr-enable;
};
/* Miscellaneous regulators */
sdcard_ext_vreg: sdcard_ext_vreg {
compatible = "regulator-fixed";
regulator-name = "sdcard_ext_vreg";
startup-delay-us = <250>;
enable-active-high;
gpio = <&pm8019_gpios 4 0>;
};
/* Rome 3.3V supply */
rome_vreg: rome_vreg {
compatible = "regulator-fixed";
regulator-name = "rome_vreg";
startup-delay-us = <4000>;
enable-active-high;
gpio = <&pm8019_gpios 3 0>;
};
emac_lan_vreg: emac_lan_vreg {
compatible = "regulator-fixed";
regulator-name = "emac_lan_vreg";
startup-delay-us = <250>;
enable-active-high;
gpio = <&pm8019_mpps 4 0>;
};
};

302
arch/arm64/boot/dts/qcom/mdm9607-rpm-regulator.dtsi Normal file
View File

@ -0,0 +1,302 @@
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&rpm_bus {
rpm-regulator-smpa1 {
qcom,resource-name = "smpa";
qcom,resource-id = <1>;
qcom,regulator-type = <1>;
qcom,hpm-min-load = <100000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-s1 {
regulator-name = "mdm9607_s1";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-smpa2 {
qcom,resource-name = "smpa";
qcom,resource-id = <2>;
qcom,regulator-type = <1>;
qcom,hpm-min-load = <100000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-s2 {
regulator-name = "mdm9607_s2";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-smpa3 {
qcom,resource-name = "smpa";
qcom,resource-id = <3>;
qcom,regulator-type = <1>;
qcom,hpm-min-load = <100000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-s3 {
regulator-name = "mdm9607_s3";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-smpa4 {
qcom,resource-name = "smpa";
qcom,resource-id = <4>;
qcom,regulator-type = <1>;
qcom,hpm-min-load = <100000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-s4 {
regulator-name = "mdm9607_s4";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-ldoa1 {
qcom,resource-name = "ldoa";
qcom,resource-id = <1>;
qcom,regulator-type = <0>;
qcom,hpm-min-load = <10000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-l1 {
regulator-name = "mdm9607_l1";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-ldoa2 {
qcom,resource-name = "ldoa";
qcom,resource-id = <2>;
qcom,regulator-type = <0>;
qcom,hpm-min-load = <5000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-l2 {
regulator-name = "mdm9607_l2";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-ldoa3 {
qcom,resource-name = "ldoa";
qcom,resource-id = <3>;
qcom,regulator-type = <0>;
qcom,hpm-min-load = <10000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-l3 {
regulator-name = "mdm9607_l3";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-ldoa4 {
qcom,resource-name = "ldoa";
qcom,resource-id = <4>;
qcom,regulator-type = <0>;
qcom,hpm-min-load = <5000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-l4 {
regulator-name = "mdm9607_l4";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-ldoa5 {
qcom,resource-name = "ldoa";
qcom,resource-id = <5>;
qcom,regulator-type = <0>;
qcom,hpm-min-load = <10000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-l5 {
regulator-name = "mdm9607_l5";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-ldoa6 {
qcom,resource-name = "ldoa";
qcom,resource-id = <6>;
qcom,regulator-type = <0>;
qcom,hpm-min-load = <10000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-l6 {
regulator-name = "mdm9607_l6";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-ldoa7 {
qcom,resource-name = "ldoa";
qcom,resource-id = <7>;
qcom,regulator-type = <0>;
qcom,hpm-min-load = <10000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-l7 {
regulator-name = "mdm9607_l7";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-ldoa8 {
qcom,resource-name = "ldoa";
qcom,resource-id = <8>;
qcom,regulator-type = <0>;
qcom,hpm-min-load = <10000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-l8 {
regulator-name = "mdm9607_l8";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-ldoa9 {
qcom,resource-name = "ldoa";
qcom,resource-id = <9>;
qcom,regulator-type = <0>;
qcom,hpm-min-load = <10000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-l9 {
regulator-name = "mdm9607_l9";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-ldoa10 {
qcom,resource-name = "ldoa";
qcom,resource-id = <10>;
qcom,regulator-type = <0>;
qcom,hpm-min-load = <10000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-l10 {
regulator-name = "mdm9607_l10";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-ldoa11 {
qcom,resource-name = "ldoa";
qcom,resource-id = <11>;
qcom,regulator-type = <0>;
qcom,hpm-min-load = <10000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-l11 {
regulator-name = "mdm9607_l11";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-ldoa12 {
qcom,resource-name = "ldoa";
qcom,resource-id = <12>;
qcom,regulator-type = <0>;
qcom,hpm-min-load = <10000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-l12 {
regulator-name = "mdm9607_l12";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-ldoa13 {
qcom,resource-name = "ldoa";
qcom,resource-id = <13>;
qcom,regulator-type = <0>;
qcom,hpm-min-load = <10000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-l13 {
regulator-name = "mdm9607_l13";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
rpm-regulator-ldoa14 {
qcom,resource-name = "ldoa";
qcom,resource-id = <14>;
qcom,regulator-type = <0>;
qcom,hpm-min-load = <10000>;
compatible = "qcom,rpm-smd-regulator-resource";
status = "disabled";
regulator-l14 {
regulator-name = "mdm9607_l14";
qcom,set = <3>;
status = "disabled";
compatible = "qcom,rpm-smd-regulator";
};
};
};

104
arch/arm64/boot/dts/qcom/mdm9607-smp2p.dtsi Normal file
View File

@ -0,0 +1,104 @@
/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&soc {
qcom,smp2p-modem {
compatible = "qcom,smp2p";
reg = <0x0b011008 0x4>;
qcom,remote-pid = <1>;
qcom,irq-bitmask = <0x4000>;
interrupts = <0 27 1>;
};
smp2pgpio_smp2p_15_in: qcom,smp2pgpio-smp2p-15-in {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <15>;
qcom,is-inbound;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
qcom,smp2pgpio_test_smp2p_15_in {
compatible = "qcom,smp2pgpio_test_smp2p_15_in";
gpios = <&smp2pgpio_smp2p_15_in 0 0>;
};
smp2pgpio_smp2p_15_out: qcom,smp2pgpio-smp2p-15-out {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <15>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
qcom,smp2pgpio_test_smp2p_15_out {
compatible = "qcom,smp2pgpio_test_smp2p_15_out";
gpios = <&smp2pgpio_smp2p_15_out 0 0>;
};
smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <1>;
qcom,is-inbound;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
qcom,smp2pgpio_test_smp2p_1_in {
compatible = "qcom,smp2pgpio_test_smp2p_1_in";
gpios = <&smp2pgpio_smp2p_1_in 0 0>;
};
smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
qcom,smp2pgpio_test_smp2p_1_out {
compatible = "qcom,smp2pgpio_test_smp2p_1_out";
gpios = <&smp2pgpio_smp2p_1_out 0 0>;
};
smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "slave-kernel";
qcom,remote-pid = <1>;
qcom,is-inbound;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "master-kernel";
qcom,remote-pid = <1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

1861
arch/arm64/boot/dts/qcom/mdm9607.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

404
arch/arm64/boot/dts/qcom/msm-pm8019.dtsi Normal file
View File

@ -0,0 +1,404 @@
/* Copyright (c) 2012,2013,2015, Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&spmi_bus {
#address-cells = <1>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <3>;
qcom,pm8019@0 {
spmi-slave-container;
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
pm8019_revid: qcom,revid@100 {
compatible = "qcom,qpnp-revid";
reg = <0x100 0x100>;
};
qcom,power_on@800 {
compatible = "qcom,qpnp-power-on";
reg = <0x800 0x100>;
interrupts = <0x0 0x8 0x2>;
interrupt-names = "cblpwr";
qcom,pon-dbc-delay = <15625>;
qcom,system-reset;
qcom,pon_1 {
qcom,pon-type = <2>;
qcom,pull-up = <1>;
linux,code = <116>;
};
};
rtc {
spmi-dev-container;
compatible = "qcom,qpnp-rtc";
#address-cells = <1>;
#size-cells = <1>;
qcom,qpnp-rtc-write = <0>;
qcom,qpnp-rtc-alarm-pwrup = <0>;
qcom,pm8019_rtc_rw@6000 {
reg = <0x6000 0x100>;
};
qcom,pm8019_rtc_alarm@6100 {
reg = <0x6100 0x100>;
interrupts = <0x0 0x61 0x1>;
};
};
pm8019_gpios: gpios {
spmi-dev-container;
compatible = "qcom,qpnp-pin";
gpio-controller;
#gpio-cells = <2>;
#address-cells = <1>;
#size-cells = <1>;
label = "pm8019-gpio";
gpio@c000 {
reg = <0xc000 0x100>;
qcom,pin-num = <1>;
};
gpio@c100 {
reg = <0xc100 0x100>;
qcom,pin-num = <2>;
};
gpio@c200 {
reg = <0xc200 0x100>;
qcom,pin-num = <3>;
};
gpio@c300 {
reg = <0xc300 0x100>;
qcom,pin-num = <4>;
};
gpio@c400 {
reg = <0xc400 0x100>;
qcom,pin-num = <5>;
};
gpio@c500 {
reg = <0xc500 0x100>;
qcom,pin-num = <6>;
};
};
pm8019_mpps: mpps {
spmi-dev-container;
compatible = "qcom,qpnp-pin";
gpio-controller;
#gpio-cells = <2>;
#address-cells = <1>;
#size-cells = <1>;
label = "pm8019-mpp";
mpp@a000 {
reg = <0xa000 0x100>;
qcom,pin-num = <1>;
};
mpp@a100 {
reg = <0xa100 0x100>;
qcom,pin-num = <2>;
};
mpp@a200 {
reg = <0xa200 0x100>;
qcom,pin-num = <3>;
};
mpp@a300 {
reg = <0xa300 0x100>;
qcom,pin-num = <4>;
};
mpp@a400 {
reg = <0xa400 0x100>;
qcom,pin-num = <5>;
};
mpp@a500 {
reg = <0xa500 0x100>;
qcom,pin-num = <6>;
};
};
pm8019_vadc: vadc@3100 {
compatible = "qcom,qpnp-vadc";
reg = <0x3100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x0 0x31 0x0>;
interrupt-names = "eoc-int-en-set";
qcom,adc-bit-resolution = <15>;
qcom,adc-vdd-reference = <1800>;
qcom,vadc-poll-eoc;
chan@8 {
label = "die_temp";
reg = <8>;
qcom,decimation = <0>;
qcom,pre-div-channel-scaling = <0>;
qcom,calibration-type = "absolute";
qcom,scale-function = <3>;
qcom,hw-settle-time = <0>;
qcom,fast-avg-setup = <0>;
};
chan@9 {
label = "ref_625mv";
reg = <9>;
qcom,decimation = <0>;
qcom,pre-div-channel-scaling = <0>;
qcom,calibration-type = "absolute";
qcom,scale-function = <0>;
qcom,hw-settle-time = <0>;
qcom,fast-avg-setup = <0>;
};
chan@a {
label = "ref_1250v";
reg = <0xa>;
qcom,decimation = <0>;
qcom,pre-div-channel-scaling = <0>;
qcom,calibration-type = "absolute";
qcom,scale-function = <0>;
qcom,hw-settle-time = <0>;
qcom,fast-avg-setup = <0>;
};
};
pm8019_adc_tm: vadc@3400 {
compatible = "qcom,qpnp-adc-tm";
reg = <0x3400 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x0 0x34 0x0>,
<0x0 0x34 0x3>,
<0x0 0x34 0x4>;
interrupt-names = "eoc-int-en-set",
"high-thr-en-set",
"low-thr-en-set";
qcom,adc-bit-resolution = <15>;
qcom,adc_tm-vadc = <&pm8019_vadc>;
qcom,adc-vdd-reference = <1800>;
};
};
qcom,pm8019@1 {
spmi-slave-container;
reg = <0x1>;
#address-cells = <1>;
#size-cells = <1>;
regulator@1400 {
regulator-name = "8019_s1";
spmi-dev-container;
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,qpnp-regulator";
reg = <0x1400 0x300>;
status = "disabled";
qcom,ctl@1400 {
reg = <0x1400 0x100>;
};
qcom,ps@1500 {
reg = <0x1500 0x100>;
};
qcom,freq@1600 {
reg = <0x1600 0x100>;
};
};
regulator@1700 {
regulator-name = "8019_s2";
spmi-dev-container;
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,qpnp-regulator";
reg = <0x1700 0x300>;
status = "disabled";
qcom,ctl@1700 {
reg = <0x1700 0x100>;
};
qcom,ps@1800 {
reg = <0x1800 0x100>;
};
qcom,freq@1900 {
reg = <0x1900 0x100>;
};
};
regulator@1a00 {
regulator-name = "8019_s3";
spmi-dev-container;
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,qpnp-regulator";
reg = <0x1a00 0x300>;
status = "disabled";
qcom,ctl@1a00 {
reg = <0x1a00 0x100>;
};
qcom,ps@1b00 {
reg = <0x1b00 0x100>;
};
qcom,freq@1c00 {
reg = <0x1c00 0x100>;
};
};
regulator@1d00 {
regulator-name = "8019_s4";
spmi-dev-container;
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,qpnp-regulator";
reg = <0x1d00 0x300>;
status = "disabled";
qcom,ctl@1d00 {
reg = <0x1d00 0x100>;
};
qcom,ps@1e00 {
reg = <0x1e00 0x100>;
};
qcom,freq@1f00 {
reg = <0x1f00 0x100>;
};
};
regulator@4000 {
regulator-name = "8019_l1";
reg = <0x4000 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
regulator@4100 {
regulator-name = "8019_l2";
reg = <0x4100 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
regulator@4200 {
regulator-name = "8019_l3";
reg = <0x4200 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
regulator@4300 {
regulator-name = "8019_l4";
reg = <0x4300 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
regulator@4400 {
regulator-name = "8019_l5";
reg = <0x4400 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
regulator@4500 {
regulator-name = "8019_l6";
reg = <0x4500 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
regulator@4600 {
regulator-name = "8019_l7";
reg = <0x4600 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
regulator@4700 {
regulator-name = "8019_l8";
reg = <0x4700 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
regulator@4800 {
regulator-name = "8019_l9";
reg = <0x4800 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
regulator@4900 {
regulator-name = "8019_l10";
reg = <0x4900 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
regulator@4a00 {
regulator-name = "8019_l11";
reg = <0x4a00 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
regulator@4b00 {
regulator-name = "8019_l12";
reg = <0x4b00 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
regulator@4c00 {
regulator-name = "8019_l13";
reg = <0x4c00 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
regulator@4d00 {
regulator-name = "8019_l14";
reg = <0x4d00 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
regulator@4e00 {
regulator-name = "8019_ldo_xo";
reg = <0x4e00 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
regulator@4f00 {
regulator-name = "8019_ldo_rfclk";
reg = <0x4f00 0x100>;
compatible = "qcom,qpnp-regulator";
status = "disabled";
};
};
};