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staging: brcm80211: replaced #ifdef __mips__ sections by W_REG_FLUSH
Code cleanup. A read-after-write construct is present in the code to ensure write order for certain Broadcom chips. Those chips are: bcm4706, bcm4716, bcm4717, bcm4718. All these chips contain a MIPS processor. This patch gets rid of several #ifdef __mips__ sections by defining a new macro in a header file. This patch does not introduce behavioral changes and is purely meant for code cleanup. The __mips__ define will be made more specific in a future patch. Signed-off-by: Roland Vossen <rvossen@broadcom.com> Reviewed-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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@ -247,16 +247,10 @@ u16 read_radio_reg(phy_info_t *pi, u16 addr)
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if ((D11REV_GE(pi->sh->corerev, 24)) ||
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(D11REV_IS(pi->sh->corerev, 22)
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&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
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W_REG(&pi->regs->radioregaddr, addr);
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#ifdef __mips__
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(void)R_REG(&pi->regs->radioregaddr);
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#endif
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W_REG_FLUSH(&pi->regs->radioregaddr, addr);
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data = R_REG(&pi->regs->radioregdata);
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} else {
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W_REG(&pi->regs->phy4waddr, addr);
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#ifdef __mips__
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(void)R_REG(&pi->regs->phy4waddr);
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#endif
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W_REG_FLUSH(&pi->regs->phy4waddr, addr);
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#ifdef __ARM_ARCH_4T__
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__asm__(" .align 4 ");
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@ -281,16 +275,10 @@ void write_radio_reg(phy_info_t *pi, u16 addr, u16 val)
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(D11REV_IS(pi->sh->corerev, 22)
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&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
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W_REG(&pi->regs->radioregaddr, addr);
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#ifdef __mips__
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(void)R_REG(&pi->regs->radioregaddr);
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#endif
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W_REG_FLUSH(&pi->regs->radioregaddr, addr);
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W_REG(&pi->regs->radioregdata, val);
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} else {
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W_REG(&pi->regs->phy4waddr, addr);
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#ifdef __mips__
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(void)R_REG(&pi->regs->phy4waddr);
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#endif
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W_REG_FLUSH(&pi->regs->phy4waddr, addr);
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W_REG(&pi->regs->phy4wdatalo, val);
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}
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@ -312,29 +300,17 @@ static u32 read_radio_id(phy_info_t *pi)
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if (D11REV_GE(pi->sh->corerev, 24)) {
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u32 b0, b1, b2;
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W_REG(&pi->regs->radioregaddr, 0);
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#ifdef __mips__
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(void)R_REG(&pi->regs->radioregaddr);
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#endif
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W_REG_FLUSH(&pi->regs->radioregaddr, 0);
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b0 = (u32) R_REG(&pi->regs->radioregdata);
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W_REG(&pi->regs->radioregaddr, 1);
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#ifdef __mips__
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(void)R_REG(&pi->regs->radioregaddr);
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#endif
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W_REG_FLUSH(&pi->regs->radioregaddr, 1);
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b1 = (u32) R_REG(&pi->regs->radioregdata);
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W_REG(&pi->regs->radioregaddr, 2);
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#ifdef __mips__
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(void)R_REG(&pi->regs->radioregaddr);
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#endif
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W_REG_FLUSH(&pi->regs->radioregaddr, 2);
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b2 = (u32) R_REG(&pi->regs->radioregdata);
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id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4)
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& 0xf);
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} else {
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W_REG(&pi->regs->phy4waddr, RADIO_IDCODE);
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#ifdef __mips__
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(void)R_REG(&pi->regs->phy4waddr);
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#endif
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W_REG_FLUSH(&pi->regs->phy4waddr, RADIO_IDCODE);
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id = (u32) R_REG(&pi->regs->phy4wdatalo);
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id |= (u32) R_REG(&pi->regs->phy4wdatahi) << 16;
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}
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@ -397,10 +373,7 @@ u16 read_phy_reg(phy_info_t *pi, u16 addr)
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regs = pi->regs;
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W_REG(®s->phyregaddr, addr);
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#ifdef __mips__
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(void)R_REG(®s->phyregaddr);
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#endif
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W_REG_FLUSH(®s->phyregaddr, addr);
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pi->phy_wreg = 0;
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return R_REG(®s->phyregdata);
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@ -413,8 +386,7 @@ void write_phy_reg(phy_info_t *pi, u16 addr, u16 val)
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regs = pi->regs;
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#ifdef __mips__
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W_REG(®s->phyregaddr, addr);
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(void)R_REG(®s->phyregaddr);
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W_REG_FLUSH(®s->phyregaddr, addr);
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W_REG(®s->phyregdata, val);
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if (addr == 0x72)
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(void)R_REG(®s->phyregdata);
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@ -436,10 +408,7 @@ void and_phy_reg(phy_info_t *pi, u16 addr, u16 val)
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regs = pi->regs;
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W_REG(®s->phyregaddr, addr);
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#ifdef __mips__
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(void)R_REG(®s->phyregaddr);
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#endif
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W_REG_FLUSH(®s->phyregaddr, addr);
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W_REG(®s->phyregdata, (R_REG(®s->phyregdata) & val));
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pi->phy_wreg = 0;
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@ -451,10 +420,7 @@ void or_phy_reg(phy_info_t *pi, u16 addr, u16 val)
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regs = pi->regs;
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W_REG(®s->phyregaddr, addr);
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#ifdef __mips__
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(void)R_REG(®s->phyregaddr);
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#endif
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W_REG_FLUSH(®s->phyregaddr, addr);
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W_REG(®s->phyregdata, (R_REG(®s->phyregdata) | val));
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pi->phy_wreg = 0;
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@ -466,10 +432,7 @@ void mod_phy_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val)
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regs = pi->regs;
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W_REG(®s->phyregaddr, addr);
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#ifdef __mips__
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(void)R_REG(®s->phyregaddr);
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#endif
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W_REG_FLUSH(®s->phyregaddr, addr);
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W_REG(®s->phyregdata,
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((R_REG(®s->phyregdata) & ~mask) | (val & mask)));
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@ -366,6 +366,17 @@ extern void bcm_prpkt(const char *msg, struct sk_buff *p0);
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} while (0)
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#endif /* __BIG_ENDIAN */
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#ifdef __mips__
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/*
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* bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder
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* transactions. As a fix, a read after write is performed on certain places
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* in the code. Older chips and the newer 5357 family don't require this fix.
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*/
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#define W_REG_FLUSH(r, v) ({ W_REG((r), (v)); (void)R_REG(r); })
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#else
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#define W_REG_FLUSH(r, v) W_REG((r), (v))
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#endif /* __mips__ */
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#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
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#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
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