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https://github.com/rd-stuffs/msm-4.14.git
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irqchip/gic: Only populate set_affinity for the root controller
Setting the affinity of an IRQ, it only applicable for the root interrupt controller and so only populate this operator for the root controller. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -384,9 +384,6 @@ static struct irq_chip gic_chip = {
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.irq_unmask = gic_unmask_irq,
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.irq_unmask = gic_unmask_irq,
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.irq_eoi = gic_eoi_irq,
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.irq_eoi = gic_eoi_irq,
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.irq_set_type = gic_set_type,
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.irq_set_type = gic_set_type,
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#ifdef CONFIG_SMP
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.irq_set_affinity = gic_set_affinity,
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#endif
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.irq_get_irqchip_state = gic_irq_get_irqchip_state,
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.irq_get_irqchip_state = gic_irq_get_irqchip_state,
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.irq_set_irqchip_state = gic_irq_set_irqchip_state,
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.irq_set_irqchip_state = gic_irq_set_irqchip_state,
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.flags = IRQCHIP_SET_TYPE_MASKED |
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.flags = IRQCHIP_SET_TYPE_MASKED |
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@ -400,9 +397,6 @@ static struct irq_chip gic_eoimode1_chip = {
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.irq_unmask = gic_unmask_irq,
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.irq_unmask = gic_unmask_irq,
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.irq_eoi = gic_eoimode1_eoi_irq,
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.irq_eoi = gic_eoimode1_eoi_irq,
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.irq_set_type = gic_set_type,
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.irq_set_type = gic_set_type,
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#ifdef CONFIG_SMP
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.irq_set_affinity = gic_set_affinity,
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#endif
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.irq_get_irqchip_state = gic_irq_get_irqchip_state,
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.irq_get_irqchip_state = gic_irq_get_irqchip_state,
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.irq_set_irqchip_state = gic_irq_set_irqchip_state,
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.irq_set_irqchip_state = gic_irq_set_irqchip_state,
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.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
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.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
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@ -1039,6 +1033,11 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
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gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr);
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gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr);
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}
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}
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#ifdef CONFIG_SMP
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if (gic_nr == 0)
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gic->chip.irq_set_affinity = gic_set_affinity;
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#endif
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#ifdef CONFIG_GIC_NON_BANKED
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#ifdef CONFIG_GIC_NON_BANKED
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if (percpu_offset) { /* Frankein-GIC without banked registers... */
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if (percpu_offset) { /* Frankein-GIC without banked registers... */
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unsigned int cpu;
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unsigned int cpu;
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