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Merge "ARM: dts: msm: Config charging termination source for PM8150B"

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qctecmdr 2019-04-04 06:36:29 -07:00 committed by Gerrit - the friendly Code Review server
commit 83d48c5b85
3 changed files with 16 additions and 1 deletions
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3
arch/arm64/boot/dts/qcom/pm8150b.dtsi
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and * it under the terms of the GNU General Public License version 2 and
@ -175,6 +175,7 @@
qcom,thermal-mitigation qcom,thermal-mitigation
= <3000000 1500000 1000000 500000>; = <3000000 1500000 1000000 500000>;
qcom,chg-term-src = <1>;
qcom,charger-temp-max = <800>; qcom,charger-temp-max = <800>;
qcom,smb-temp-max = <800>; qcom,smb-temp-max = <800>;

9
drivers/power/supply/qcom/qpnp-smb5.c
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@ -2232,9 +2232,18 @@ static int smb5_configure_iterm_thresholds_adc(struct smb5 *chip)
static int smb5_configure_iterm_thresholds(struct smb5 *chip) static int smb5_configure_iterm_thresholds(struct smb5 *chip)
{ {
int rc = 0; int rc = 0;
struct smb_charger *chg = &chip->chg;
switch (chip->dt.term_current_src) { switch (chip->dt.term_current_src) {
case ITERM_SRC_ADC: case ITERM_SRC_ADC:
rc = smblib_masked_write(chg, CHGR_ADC_TERM_CFG_REG,
TERM_BASED_ON_SYNC_CONV_OR_SAMPLE_CNT,
TERM_BASED_ON_SAMPLE_CNT);
if (rc < 0) {
dev_err(chg->dev, "Couldn't configure ADC_ITERM_CFG rc=%d\n",
rc);
return rc;
}
rc = smb5_configure_iterm_thresholds_adc(chip); rc = smb5_configure_iterm_thresholds_adc(chip);
break; break;
default: default:

5
drivers/power/supply/qcom/smb5-reg.h
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@ -86,6 +86,11 @@ enum {
#define NO_OF_SAMPLE_FOR_RCHG_SHIFT 2 #define NO_OF_SAMPLE_FOR_RCHG_SHIFT 2
#define NO_OF_SAMPLE_FOR_RCHG GENMASK(3, 2) #define NO_OF_SAMPLE_FOR_RCHG GENMASK(3, 2)
#define CHGR_ADC_TERM_CFG_REG (CHGR_BASE + 0x6C)
#define TERM_BASED_ON_SYNC_CONV_OR_SAMPLE_CNT BIT(0)
#define TERM_BASED_ON_SYNC_CONV 0
#define TERM_BASED_ON_SAMPLE_CNT 1
#define CHGR_FLOAT_VOLTAGE_CFG_REG (CHGR_BASE + 0x70) #define CHGR_FLOAT_VOLTAGE_CFG_REG (CHGR_BASE + 0x70)
#define CHARGE_INHIBIT_THRESHOLD_CFG_REG (CHGR_BASE + 0x72) #define CHARGE_INHIBIT_THRESHOLD_CFG_REG (CHGR_BASE + 0x72)