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clockevents/drivers/atmel-st: Migrate to new 'set-state' interface
Migrate atmel-st driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Tested-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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@ -106,36 +106,47 @@ static struct clocksource clk32k = {
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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};
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static void
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static void clkdev32k_disable_and_flush_irq(void)
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clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
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{
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{
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unsigned int val;
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unsigned int val;
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/* Disable and flush pending timer interrupts */
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/* Disable and flush pending timer interrupts */
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regmap_write(regmap_st, AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
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regmap_write(regmap_st, AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
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regmap_read(regmap_st, AT91_ST_SR, &val);
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regmap_read(regmap_st, AT91_ST_SR, &val);
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last_crtr = read_CRTR();
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last_crtr = read_CRTR();
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switch (mode) {
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}
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case CLOCK_EVT_MODE_PERIODIC:
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/* PIT for periodic irqs; fixed rate of 1/HZ */
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static int clkevt32k_shutdown(struct clock_event_device *evt)
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irqmask = AT91_ST_PITS;
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{
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regmap_write(regmap_st, AT91_ST_PIMR, RM9200_TIMER_LATCH);
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clkdev32k_disable_and_flush_irq();
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break;
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irqmask = 0;
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case CLOCK_EVT_MODE_ONESHOT:
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/* ALM for oneshot irqs, set by next_event()
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* before 32 seconds have passed
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*/
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irqmask = AT91_ST_ALMS;
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regmap_write(regmap_st, AT91_ST_RTAR, last_crtr);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_RESUME:
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irqmask = 0;
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break;
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}
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regmap_write(regmap_st, AT91_ST_IER, irqmask);
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regmap_write(regmap_st, AT91_ST_IER, irqmask);
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return 0;
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}
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static int clkevt32k_set_oneshot(struct clock_event_device *dev)
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{
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clkdev32k_disable_and_flush_irq();
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/*
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* ALM for oneshot irqs, set by next_event()
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* before 32 seconds have passed.
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*/
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irqmask = AT91_ST_ALMS;
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regmap_write(regmap_st, AT91_ST_RTAR, last_crtr);
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regmap_write(regmap_st, AT91_ST_IER, irqmask);
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return 0;
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}
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static int clkevt32k_set_periodic(struct clock_event_device *dev)
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{
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clkdev32k_disable_and_flush_irq();
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/* PIT for periodic irqs; fixed rate of 1/HZ */
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irqmask = AT91_ST_PITS;
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regmap_write(regmap_st, AT91_ST_PIMR, RM9200_TIMER_LATCH);
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regmap_write(regmap_st, AT91_ST_IER, irqmask);
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return 0;
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}
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}
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static int
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static int
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@ -170,11 +181,15 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
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}
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}
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static struct clock_event_device clkevt = {
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static struct clock_event_device clkevt = {
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.name = "at91_tick",
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.name = "at91_tick",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.features = CLOCK_EVT_FEAT_PERIODIC |
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.rating = 150,
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CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = clkevt32k_next_event,
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.rating = 150,
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.set_mode = clkevt32k_mode,
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.set_next_event = clkevt32k_next_event,
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.set_state_shutdown = clkevt32k_shutdown,
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.set_state_periodic = clkevt32k_set_periodic,
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.set_state_oneshot = clkevt32k_set_oneshot,
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.tick_resume = clkevt32k_shutdown,
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};
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};
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/*
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/*
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