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MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.

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This extends commit a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d to cover
MIPSxx-style board cache code.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Kevin Cernekee 2009-09-18 19:12:45 -07:00 committed by Ralf Baechle
parent a648e81196
commit 96983ffefc
1 changed files with 5 additions and 0 deletions
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5
arch/mips/mm/sc-mips.c
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@ -32,6 +32,11 @@ static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
*/
static void mips_sc_inv(unsigned long addr, unsigned long size)
{
unsigned long lsize = cpu_scache_line_size();
unsigned long almask = ~(lsize - 1);
cache_op(Hit_Writeback_Inv_SD, addr & almask);
cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
blast_inv_scache_range(addr, addr + size);
}