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Merge "drm/msm/dp: disable back-pressure before starting stream" into dev/msm-4.14-display

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Linux Build Service Account 2018-07-27 13:37:03 -07:00 committed by Gerrit - the friendly Code Review server
commit 9bd2e57e7d
6 changed files with 52 additions and 8 deletions
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35
drivers/gpu/drm/msm/dp/dp_catalog.c
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@ -782,6 +782,40 @@ static void dp_catalog_panel_config_ctrl(struct dp_catalog_panel *panel,
dp_write(catalog, io_data, MMSS_DP_ASYNC_FIFO_CONFIG, 0x00);
}
static void dp_catalog_panel_config_dto(struct dp_catalog_panel *panel,
bool ack)
{
struct dp_catalog_private *catalog;
struct dp_io_data *io_data;
if (!panel) {
pr_err("invalid input\n");
return;
}
if (panel->stream_id >= DP_STREAM_MAX) {
pr_err("invalid stream_id:%d\n", panel->stream_id);
return;
}
catalog = dp_catalog_get_priv(panel);
io_data = catalog->io.dp_link;
switch (panel->stream_id) {
case DP_STREAM_0:
io_data = catalog->io.dp_p0;
break;
case DP_STREAM_1:
io_data = catalog->io.dp_p1;
break;
default:
pr_err("invalid stream id\n");
return;
}
dp_write(catalog, io_data, MMSS_DP_DSC_DTO, ack << 1);
}
static void dp_catalog_ctrl_lane_mapping(struct dp_catalog_ctrl *ctrl)
{
struct dp_catalog_private *catalog;
@ -2182,6 +2216,7 @@ struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_parser *parser)
.config_msa = dp_catalog_panel_config_msa,
.update_transfer_unit = dp_catalog_panel_update_transfer_unit,
.config_ctrl = dp_catalog_panel_config_ctrl,
.config_dto = dp_catalog_panel_config_dto,
};
if (!dev || !parser) {

1
drivers/gpu/drm/msm/dp/dp_catalog.h
View File

@ -205,6 +205,7 @@ struct dp_catalog_panel {
u32 rate, u32 stream_rate_khz, bool fixed_nvid);
void (*update_transfer_unit)(struct dp_catalog_panel *panel);
void (*config_ctrl)(struct dp_catalog_panel *panel, u32 cfg);
void (*config_dto)(struct dp_catalog_panel *panel, bool ack);
};
struct dp_catalog;

4
drivers/gpu/drm/msm/dp/dp_ctrl.c
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@ -985,7 +985,7 @@ static int dp_ctrl_stream_on(struct dp_ctrl *dp_ctrl, struct dp_panel *panel)
return 0;
}
rc = panel->hw_cfg(panel);
rc = panel->hw_cfg(panel, true);
if (rc)
return rc;
@ -1059,6 +1059,8 @@ static void dp_ctrl_stream_off(struct dp_ctrl *dp_ctrl, struct dp_panel *panel)
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
panel->hw_cfg(panel, false);
dp_ctrl_disable_stream_clocks(ctrl, panel);
}

16
drivers/gpu/drm/msm/dp/dp_panel.c
View File

@ -1525,7 +1525,7 @@ static void dp_panel_config_msa(struct dp_panel *dp_panel)
catalog->config_msa(catalog, rate, stream_rate_khz, fixed_nvid);
}
static int dp_panel_hw_cfg(struct dp_panel *dp_panel)
static int dp_panel_hw_cfg(struct dp_panel *dp_panel, bool enable)
{
struct dp_panel_private *panel;
@ -1542,11 +1542,15 @@ static int dp_panel_hw_cfg(struct dp_panel *dp_panel)
panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
panel->catalog->stream_id = dp_panel->stream_id;
dp_panel_config_ctrl(dp_panel);
dp_panel_config_misc(dp_panel);
dp_panel_config_msa(dp_panel);
dp_panel_config_tr_unit(dp_panel);
dp_panel_config_timing(dp_panel);
if (enable) {
dp_panel_config_ctrl(dp_panel);
dp_panel_config_misc(dp_panel);
dp_panel_config_msa(dp_panel);
dp_panel_config_tr_unit(dp_panel);
dp_panel_config_timing(dp_panel);
}
panel->catalog->config_dto(panel->catalog, !enable);
return 0;
}

2
drivers/gpu/drm/msm/dp/dp_panel.h
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@ -100,7 +100,7 @@ struct dp_panel {
int (*init)(struct dp_panel *dp_panel);
int (*deinit)(struct dp_panel *dp_panel);
int (*hw_cfg)(struct dp_panel *dp_panel);
int (*hw_cfg)(struct dp_panel *dp_panel, bool enable);
int (*read_sink_caps)(struct dp_panel *dp_panel,
struct drm_connector *connector, bool multi_func);
u32 (*get_min_req_link_rate)(struct dp_panel *dp_panel);

2
drivers/gpu/drm/msm/dp/dp_reg.h
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@ -222,6 +222,7 @@
#define MMSS_DP_INTF_POLARITY_CTL (0x00000058)
#define MMSS_DP_TPG_MAIN_CONTROL (0x00000060)
#define MMSS_DP_TPG_VIDEO_CONFIG (0x00000064)
#define MMSS_DP_DSC_DTO (0x0000007C)
#define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088)
#define MMSS_DP1_BIST_ENABLE (0x00000000)
@ -245,6 +246,7 @@
#define MMSS_DP1_INTF_POLARITY_CTL (0x00000058)
#define MMSS_DP1_TPG_MAIN_CONTROL (0x00000060)
#define MMSS_DP1_TPG_VIDEO_CONFIG (0x00000064)
#define MMSS_DP1_DSC_DTO (0x0000007C)
#define MMSS_DP1_ASYNC_FIFO_CONFIG (0x00000088)
/*DP PHY Register offsets */