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Merge branch 'drm-fixes-3.10' of git://people.freedesktop.org/~agd5f/linux into drm-next

Browse Source 
Minor bug fixes.

* 'drm-fixes-3.10' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon/dce2: use 10khz units for audio dto calculation
  drm/radeon: Fix VRAM size calculation for VRAM >= 4GB
  drm/radeon: Remove superfluous variable
This commit is contained in:
Dave Airlie 2013-05-21 09:41:33 +10:00
commit a3f6902672
8 changed files with 12 additions and 25 deletions
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6
drivers/gpu/drm/radeon/atombios_crtc.c
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@ -1811,12 +1811,9 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
static void atombios_crtc_prepare(struct drm_crtc *crtc) static void atombios_crtc_prepare(struct drm_crtc *crtc)
{ {
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct radeon_device *rdev = dev->dev_private; struct radeon_device *rdev = dev->dev_private;
radeon_crtc->in_mode_set = true;
/* disable crtc pair power gating before programming */ /* disable crtc pair power gating before programming */
if (ASIC_IS_DCE6(rdev)) if (ASIC_IS_DCE6(rdev))
atombios_powergate_crtc(crtc, ATOM_DISABLE); atombios_powergate_crtc(crtc, ATOM_DISABLE);
@ -1827,11 +1824,8 @@ static void atombios_crtc_prepare(struct drm_crtc *crtc)
static void atombios_crtc_commit(struct drm_crtc *crtc) static void atombios_crtc_commit(struct drm_crtc *crtc)
{ {
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
atombios_lock_crtc(crtc, ATOM_DISABLE); atombios_lock_crtc(crtc, ATOM_DISABLE);
radeon_crtc->in_mode_set = false;
} }
static void atombios_crtc_disable(struct drm_crtc *crtc) static void atombios_crtc_disable(struct drm_crtc *crtc)

4
drivers/gpu/drm/radeon/evergreen.c
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@ -3405,8 +3405,8 @@ int evergreen_mc_init(struct radeon_device *rdev)
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
} else { } else {
/* size in MB on evergreen/cayman/tn */ /* size in MB on evergreen/cayman/tn */
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
} }
rdev->mc.visible_vram_size = rdev->mc.aper_size; rdev->mc.visible_vram_size = rdev->mc.aper_size;
r700_vram_gtt_location(rdev, &rdev->mc); r700_vram_gtt_location(rdev, &rdev->mc);

7
drivers/gpu/drm/radeon/evergreen_hdmi.c
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@ -154,19 +154,18 @@ static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
u32 base_rate = 48000; u32 base_rate = 24000;
if (!dig || !dig->afmt) if (!dig || !dig->afmt)
return; return;
/* XXX: properly calculate this */
/* XXX two dtos; generally use dto0 for hdmi */ /* XXX two dtos; generally use dto0 for hdmi */
/* Express [24MHz / target pixel clock] as an exact rational /* Express [24MHz / target pixel clock] as an exact rational
* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
*/ */
WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff); WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff); WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id)); WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
} }

9
drivers/gpu/drm/radeon/r600_hdmi.c
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@ -232,7 +232,7 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
struct radeon_device *rdev = dev->dev_private; struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
u32 base_rate = 48000; u32 base_rate = 24000;
if (!dig || !dig->afmt) if (!dig || !dig->afmt)
return; return;
@ -240,7 +240,6 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
/* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
* doesn't matter which one you use. Just use the first one. * doesn't matter which one you use. Just use the first one.
*/ */
/* XXX: properly calculate this */
/* XXX two dtos; generally use dto0 for hdmi */ /* XXX two dtos; generally use dto0 for hdmi */
/* Express [24MHz / target pixel clock] as an exact rational /* Express [24MHz / target pixel clock] as an exact rational
* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
@ -250,13 +249,13 @@ void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
/* according to the reg specs, this should DCE3.2 only, but in /* according to the reg specs, this should DCE3.2 only, but in
* practice it seems to cover DCE3.0 as well. * practice it seems to cover DCE3.0 as well.
*/ */
WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 50); WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
} else { } else {
/* according to the reg specs, this should be DCE2.0 and DCE3.0 */ /* according to the reg specs, this should be DCE2.0 and DCE3.0 */
WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate * 50) | WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) |
AUDIO_DTO_MODULE(clock * 100)); AUDIO_DTO_MODULE(clock / 10));
} }
} }

4
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
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@ -1031,11 +1031,9 @@ static int radeon_crtc_mode_set(struct drm_crtc *crtc,
static void radeon_crtc_prepare(struct drm_crtc *crtc) static void radeon_crtc_prepare(struct drm_crtc *crtc)
{ {
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_crtc *crtci; struct drm_crtc *crtci;
radeon_crtc->in_mode_set = true;
/* /*
* The hardware wedges sometimes if you reconfigure one CRTC * The hardware wedges sometimes if you reconfigure one CRTC
* whilst another is running (see fdo bug #24611). * whilst another is running (see fdo bug #24611).
@ -1046,7 +1044,6 @@ static void radeon_crtc_prepare(struct drm_crtc *crtc)
static void radeon_crtc_commit(struct drm_crtc *crtc) static void radeon_crtc_commit(struct drm_crtc *crtc)
{ {
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_crtc *crtci; struct drm_crtc *crtci;
@ -1057,7 +1054,6 @@ static void radeon_crtc_commit(struct drm_crtc *crtc)
if (crtci->enabled) if (crtci->enabled)
radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
} }
radeon_crtc->in_mode_set = false;
} }
static const struct drm_crtc_helper_funcs legacy_helper_funcs = { static const struct drm_crtc_helper_funcs legacy_helper_funcs = {

1
drivers/gpu/drm/radeon/radeon_mode.h
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@ -302,7 +302,6 @@ struct radeon_crtc {
u16 lut_r[256], lut_g[256], lut_b[256]; u16 lut_r[256], lut_g[256], lut_b[256];
bool enabled; bool enabled;
bool can_tile; bool can_tile;
bool in_mode_set;
uint32_t crtc_offset; uint32_t crtc_offset;
struct drm_gem_object *cursor_bo; struct drm_gem_object *cursor_bo;
uint64_t cursor_addr; uint64_t cursor_addr;

2
drivers/gpu/drm/radeon/radeon_ttm.c
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@ -726,7 +726,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
return r; return r;
} }
DRM_INFO("radeon: %uM of VRAM memory ready\n", DRM_INFO("radeon: %uM of VRAM memory ready\n",
(unsigned)rdev->mc.real_vram_size / (1024 * 1024)); (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
rdev->mc.gtt_size >> PAGE_SHIFT); rdev->mc.gtt_size >> PAGE_SHIFT);
if (r) { if (r) {

4
drivers/gpu/drm/radeon/si.c
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@ -3397,8 +3397,8 @@ static int si_mc_init(struct radeon_device *rdev)
rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
/* size in MB on si */ /* size in MB on si */
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
rdev->mc.visible_vram_size = rdev->mc.aper_size; rdev->mc.visible_vram_size = rdev->mc.aper_size;
si_vram_gtt_location(rdev, &rdev->mc); si_vram_gtt_location(rdev, &rdev->mc);
radeon_update_bandwidth_info(rdev); radeon_update_bandwidth_info(rdev);