malhuda/msm-4.14
1
0
Fork 0
mirror of https://github.com/rd-stuffs/msm-4.14.git synced 2025-02-20 11:45:48 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

qos: Change cpus_affine to not be atomic

Browse Source 
There isn't a need for cpus_affine to be atomic, and reading/writing to
it outside of the global pm_qos lock is racy anyway. As such, we can
simply turn it into a primitive integer type.

Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
Signed-off-by: azrim <mirzaspc@gmail.com>
This commit is contained in:
Sultan Alsawaf 2021-10-17 23:50:38 -07:00 committed by azrim
parent 7978c43d40
commit b785b90d42
No known key found for this signature in database
GPG Key ID: 497F8FB059B45D1C
6 changed files with 19 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/drm_atomic.c
View File

@ -2388,7 +2388,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, void *data,
*/
struct pm_qos_request req = {
.type = PM_QOS_REQ_AFFINE_CORES,
.cpus_affine = ATOMIC_INIT(BIT(raw_smp_processor_id()))
.cpus_affine = BIT(raw_smp_processor_id())
};
int ret;

2
drivers/gpu/drm/msm/sde/sde_encoder.c
View File

@ -313,7 +313,7 @@ static void _sde_encoder_pm_qos_add_request(struct drm_encoder *drm_enc,
req = &sde_enc->pm_qos_cpu_req;
req->type = PM_QOS_REQ_AFFINE_CORES;
atomic_set(&req->cpus_affine, cpu_mask);
req->cpus_affine, cpu_mask;
pm_qos_add_request(req, PM_QOS_CPU_DMA_LATENCY, cpu_dma_latency);
SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu_mask, cpu_dma_latency);

2
drivers/gpu/msm/kgsl_ioctl.c
View File

@ -205,7 +205,7 @@ long kgsl_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
*/
struct pm_qos_request req = {
.type = PM_QOS_REQ_AFFINE_CORES,
.cpus_affine = ATOMIC_INIT(BIT(raw_smp_processor_id()))
.cpus_affine = BIT(raw_smp_processor_id())
};
long ret;

12
drivers/mmc/host/sdhci-msm.c
View File

@ -4162,8 +4162,8 @@ void sdhci_msm_pm_qos_irq_init(struct sdhci_host *host)
(msm_host->pm_qos_irq.req.type != PM_QOS_REQ_ALL_CORES))
set_affine_irq(msm_host, host);
else
atomic_set(&msm_host->pm_qos_irq.req.cpus_affine,
msm_host->pdata->pm_qos_data.irq_cpu);
msm_host->pm_qos_irq.req.cpus_affine,
msm_host->pdata->pm_qos_data.irq_cpu;
sdhci_msm_pm_qos_wq_init(msm_host);
@ -4218,7 +4218,7 @@ static ssize_t sdhci_msm_pm_qos_group_show(struct device *dev,
group = &msm_host->pm_qos[i];
offset += snprintf(&buf[offset], PAGE_SIZE,
"Group #%d (mask=0x%d) PM QoS: enabled=%d, counter=%d, latency=%d\n",
i, atomic_read(&group->req.cpus_affine),
i, group->req.cpus_affine,
msm_host->pm_qos_group_enable,
atomic_read(&group->counter),
group->latency);
@ -4377,15 +4377,15 @@ void sdhci_msm_pm_qos_cpu_init(struct sdhci_host *host,
sdhci_msm_pm_qos_cpu_unvote_work);
atomic_set(&group->counter, 0);
group->req.type = PM_QOS_REQ_AFFINE_CORES;
atomic_set(&group->req.cpus_affine,
*cpumask_bits(&msm_host->pdata->pm_qos_data.cpu_group_map.mask[i]));
group->req.cpus_affine,
*cpumask_bits(&msm_host->pdata->pm_qos_data.cpu_group_map.mask[i]);
/* We set default latency here for all pm_qos cpu groups. */
group->latency = PM_QOS_DEFAULT_VALUE;
pm_qos_add_request(&group->req, PM_QOS_CPU_DMA_LATENCY,
group->latency);
pr_info("%s (): voted for group #%d (mask=0x%d) latency=%d\n",
__func__, i,
atomic_read(&group->req.cpus_affine),
group->req.cpus_affine,
group->latency);
}
msm_host->pm_qos_prev_cpu = -1;

2
include/linux/pm_qos.h
View File

@ -53,8 +53,8 @@ enum pm_qos_req_type {
};
struct pm_qos_request {
unsigned long cpus_affine;
enum pm_qos_req_type type;
atomic_t cpus_affine;
#ifdef CONFIG_SMP
uint32_t irq;
/* Internal structure members */

17
kernel/power/qos.c
View File

@ -284,7 +284,7 @@ static inline int pm_qos_set_value_for_cpus(struct pm_qos_constraints *c,
return -EINVAL;
plist_for_each_entry(req, &c->list, node) {
unsigned long affined_cpus = atomic_read(&req->cpus_affine);
unsigned long affined_cpus = req->cpus_affine;
for_each_cpu(cpu, to_cpumask(&affined_cpus)) {
switch (c->type) {
@ -541,7 +541,7 @@ static void pm_qos_irq_release(struct kref *ref)
struct pm_qos_constraints *c =
pm_qos_array[req->pm_qos_class]->constraints;
atomic_set(&req->cpus_affine, CPUMASK_ALL);
req->cpus_affine = CPUMASK_ALL;
pm_qos_update_target(c, &req->node, PM_QOS_UPDATE_REQ,
c->default_value);
}
@ -554,7 +554,7 @@ static void pm_qos_irq_notify(struct irq_affinity_notify *notify,
struct pm_qos_constraints *c =
pm_qos_array[req->pm_qos_class]->constraints;
atomic_set(&req->cpus_affine, *cpumask_bits(mask));
req->cpus_affine = CPUMASK_ALL;
pm_qos_update_target(c, &req->node, PM_QOS_UPDATE_REQ, req->node.prio);
}
#endif
@ -585,7 +585,8 @@ void pm_qos_add_request(struct pm_qos_request *req,
switch (req->type) {
case PM_QOS_REQ_AFFINE_CORES:
if (!atomic_cmpxchg_relaxed(&req->cpus_affine, 0, CPUMASK_ALL)) {
if (!req->cpus_affine) {
req->cpus_affine = CPUMASK_ALL;
req->type = PM_QOS_REQ_ALL_CORES;
WARN(1, "Affine cores not set for request with affinity flag\n");
}
@ -602,14 +603,14 @@ void pm_qos_add_request(struct pm_qos_request *req,
mask = desc->irq_data.common->affinity;
/* Get the current affinity */
atomic_set(&req->cpus_affine, *cpumask_bits(mask));
req->cpus_affine = *cpumask_bits(mask);
req->irq_notify.irq = req->irq;
req->irq_notify.notify = pm_qos_irq_notify;
req->irq_notify.release = pm_qos_irq_release;
} else {
req->type = PM_QOS_REQ_ALL_CORES;
atomic_set(&req->cpus_affine, CPUMASK_ALL);
req->cpus_affine = CPUMASK_ALL;
WARN(1, "IRQ-%d not set for request with affinity flag\n",
req->irq);
}
@ -619,7 +620,7 @@ void pm_qos_add_request(struct pm_qos_request *req,
WARN(1, "Unknown request type %d\n", req->type);
/* fall through */
case PM_QOS_REQ_ALL_CORES:
atomic_set(&req->cpus_affine, CPUMASK_ALL);
req->cpus_affine = CPUMASK_ALL;
break;
}
@ -639,7 +640,7 @@ void pm_qos_add_request(struct pm_qos_request *req,
if (ret) {
WARN(1, "IRQ affinity notify set failed\n");
req->type = PM_QOS_REQ_ALL_CORES;
atomic_set(&req->cpus_affine, CPUMASK_ALL);
req->cpus_affine = CPUMASK_ALL;
pm_qos_update_target(
pm_qos_array[pm_qos_class]->constraints,
&req->node, PM_QOS_UPDATE_REQ, value);