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edac: Check part number before parsing L1/L2 error
Parse L1/L2 errors based on the part number. This will remove the need for keeping track of the number of cores in cluster, boot core etc. Change-Id: Idcaeff7ff1a82b8f52344588a5ab53f087bc439e Signed-off-by: Prateek Sood <prsood@codeaurora.org>
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@ -46,8 +46,12 @@ module_param(poll_msec, int, 0444);
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#define L2_SILVER_BIT 0x1
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#define L3_BIT 0x2
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#define L1_GOLD_DC_BIT 0x1
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#define L1_GOLD_IC_BIT 0x4
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#define QCOM_CPU_PART_KRYO4XX_GOLD 0x804
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#define QCOM_CPU_PART_KRYO4XX_SILVER_V1 0x803
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#define QCOM_CPU_PART_KRYO4XX_SILVER_V2 0x805
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#define L1_GOLD_IC_BIT 0x1
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#define L1_GOLD_DC_BIT 0x4
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#define L2_GOLD_BIT 0x8
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#define L2_GOLD_TLB_BIT 0x2
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@ -258,8 +262,12 @@ static void kryo_parse_l1_l2_cache_error(u64 errxstatus, u64 errxmisc,
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struct edac_device_ctl_info *edev_ctl, int cpu)
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{
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int level = 0;
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u32 part_num;
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if (cpu <= 3) {
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part_num = read_cpuid_part_number();
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switch (part_num) {
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case QCOM_CPU_PART_KRYO4XX_SILVER_V1:
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case QCOM_CPU_PART_KRYO4XX_SILVER_V2:
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switch (KRYO_ERRXMISC_LVL(errxmisc)) {
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case L1_SILVER_BIT:
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level = L1;
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@ -267,8 +275,13 @@ static void kryo_parse_l1_l2_cache_error(u64 errxstatus, u64 errxmisc,
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case L2_SILVER_BIT:
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level = L2;
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break;
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default:
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edac_printk(KERN_CRIT, EDAC_CPU,
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"silver cpu:%d unknown error location:%u\n",
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cpu, KRYO_ERRXMISC_LVL(errxmisc));
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}
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} else {
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break;
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case QCOM_CPU_PART_KRYO4XX_GOLD:
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switch (KRYO_ERRXMISC_LVL_GOLD(errxmisc)) {
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case L1_GOLD_DC_BIT:
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case L1_GOLD_IC_BIT:
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@ -278,8 +291,19 @@ static void kryo_parse_l1_l2_cache_error(u64 errxstatus, u64 errxmisc,
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case L2_GOLD_TLB_BIT:
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level = L2;
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break;
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default:
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edac_printk(KERN_CRIT, EDAC_CPU,
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"gold cpu:%d unknown error location:%u\n",
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cpu, KRYO_ERRXMISC_LVL_GOLD(errxmisc));
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}
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break;
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default:
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edac_printk(KERN_CRIT, EDAC_CPU,
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"Error in matching cpu%d with part num:%u\n",
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cpu, part_num);
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return;
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}
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switch (level) {
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case L1:
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if (KRYO_ERRXSTATUS_UE(errxstatus))
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