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clk: qcom: npucc-sm8150: Minor change to the CRC enable sequence

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As part of the CRC enable sequence for the npu_cc_cal_dp_clk_src
RCG, the clock driver currently sets the RCGs rate to the VDD_MIN
frequency. However, that's not a corner that's supported on all
versions of the target. Set the RCG to the lowest supported
frequency instead.

Change-Id: I2c318a2b5870fc7ab2ea1481235725fc4eb9a7d0
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
This commit is contained in:
Deepak Katragadda 2018-05-30 11:50:17 -07:00
parent 9ee8946479
commit beb3e1828e
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/qcom/npucc-sm8150.c
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@ -603,9 +603,9 @@ static int enable_npu_crc(struct regmap *regmap)
{
int ret = 0;
/* Set npu_cc_cal_cp_clk to a safe frequency */
/* Set npu_cc_cal_cp_clk to the lowest supported frequency */
clk_set_rate(npu_cc_cal_dp_clk.clkr.hw.clk,
npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_MIN]);
clk_round_rate(npu_cc_cal_dp_clk_src.clkr.hw.clk, 1));
/* Turn on the NPU GDSC */
ret = regulator_enable(vdd_gdsc);
if (ret) {