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Merge "defconfig: qcs405: Enable watchdog configs for QCS405"

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qctecmdr Service 2018-06-28 07:57:48 -07:00 committed by Gerrit - the friendly Code Review server
commit c40ef1a460
5 changed files with 22 additions and 2 deletions
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1
Documentation/devicetree/bindings/pil/subsys-pil-tz.txt
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@ -71,6 +71,7 @@ Optional properties:
- qcom,signal-aop: Boolean. If set, when subsystem is brought up, pil will send a notification
to AOP through qmp mailbox driver.
- qcom,mas-crypto: phandle to the bus master of crypto core.
Example:
qcom,venus@fdce0000 {

3
arch/arm/configs/vendor/qcs405_defconfig vendored
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@ -404,6 +404,9 @@ CONFIG_QCOM_SMD_RPM=y
CONFIG_MSM_SPM=y
CONFIG_MSM_L2_SPM=y
CONFIG_QCOM_SCM=y
CONFIG_QCOM_WATCHDOG_V2=y
CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
CONFIG_QCOM_WDOG_IPI_ENABLE=y
CONFIG_QCOM_SMP2P=y
CONFIG_MSM_SERVICE_LOCATOR=y
CONFIG_MSM_SERVICE_NOTIFIER=y

3
arch/arm64/boot/dts/qcom/qcs405.dtsi
View File

@ -450,6 +450,7 @@
qcom,proxy-clock-names = "xo";
qcom,pas-id = <1>;
qcom,mas-crypto = <&mas_crypto>;
qcom,complete-ramdump;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <423>;
@ -488,6 +489,7 @@
qcom,proxy-clock-names = "xo";
qcom,pas-id = <18>;
qcom,mas-crypto = <&mas_crypto>;
qcom,complete-ramdump;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <601>;
@ -526,6 +528,7 @@
qcom,proxy-clock-names = "xo";
qcom,pas-id = <6>;
qcom,mas-crypto = <&mas_crypto>;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <422>;
qcom,sysmon-id = <0>;

3
arch/arm64/configs/vendor/qcs405_defconfig vendored
View File

@ -404,6 +404,9 @@ CONFIG_QCOM_SMD_RPM=y
CONFIG_MSM_SPM=y
CONFIG_MSM_L2_SPM=y
CONFIG_QCOM_SCM=y
CONFIG_QCOM_WATCHDOG_V2=y
CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y
CONFIG_QCOM_WDOG_IPI_ENABLE=y
CONFIG_QCOM_SMP2P=y
CONFIG_MSM_SERVICE_LOCATOR=y
CONFIG_MSM_SERVICE_NOTIFIER=y

14
drivers/soc/qcom/subsys-pil-tz.c
View File

@ -1031,7 +1031,8 @@ static int pil_tz_driver_probe(struct platform_device *pdev)
{
struct pil_tz_data *d;
struct resource *res;
u32 proxy_timeout;
struct device_node *crypto_node;
u32 proxy_timeout, crypto_id;
int len, rc;
d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
@ -1087,7 +1088,16 @@ static int pil_tz_driver_probe(struct platform_device *pdev)
rc);
return rc;
}
scm_pas_init(MSM_BUS_MASTER_CRYPTO_CORE_0);
crypto_id = MSM_BUS_MASTER_CRYPTO_CORE_0;
crypto_node = of_parse_phandle(pdev->dev.of_node,
"qcom,mas-crypto", 0);
if (!IS_ERR_OR_NULL(crypto_node)) {
of_property_read_u32(crypto_node, "cell-id",
&crypto_id);
}
of_node_put(crypto_node);
scm_pas_init((int)crypto_id);
}
rc = pil_desc_init(&d->desc);