malhuda/msm-4.14
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Merge changes I372d4e8d,Idd7c2fdc,I0381321d,I3aa636ca,I4c6be6cb into msm-4.14

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* changes:
  ARM: dts: msm: Add devicetree overlay files for sdmshrike
  ARM: dts: msm: Add CPUSS core hang dt node for sdmshrike
  ARM: dts: msm: Add L1 cache definitions to sdmshrike target
  defconfig: Enable POWEROFF driver on sdmshrike target
  ARM: dts: msm: Update interrupt parent and smp2p bits for LPASS
This commit is contained in:
Linux Build Service Account 2018-04-13 11:31:54 -07:00 committed by Gerrit - the friendly Code Review server
commit c82bc68f83
7 changed files with 275 additions and 5 deletions
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9
arch/arm64/boot/dts/qcom/Makefile
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@ -36,9 +36,18 @@ dtb-$(CONFIG_ARCH_SM8150) += sm8150-rumi.dtb \
sm8150-v2-qrd.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_SDMSHRIKE) += \
sdmshrike-cdp-overlay.dtbo \
sdmshrike-mtp-overlay.dtbo
sdmshrike-cdp-overlay.dtbo-base := sdmshrike.dtb
sdmshrike-mtp-overlay.dtbo-base := sdmshrike.dtb
else
dtb-$(CONFIG_ARCH_SDMSHRIKE) += sdmshrike-rumi.dtb \
sdmshrike-mtp.dtb \
sdmshrike-cdp.dtb
endif
ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
dtbo-$(CONFIG_ARCH_SDM640) += \

26
arch/arm64/boot/dts/qcom/sdmshrike-cdp-overlay.dts Normal file
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@ -0,0 +1,26 @@
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,gcc-sdmshrike.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "sdmshrike-cdp.dtsi"
/ {
model = "CDP";
compatible = "qcom,sdmshrike-cdp", "qcom,sdmshrike", "qcom,cdp";
qcom,board-id = <1 0>;
};

26
arch/arm64/boot/dts/qcom/sdmshrike-mtp-overlay.dts Normal file
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@ -0,0 +1,26 @@
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/clock/qcom,gcc-sdmshrike.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "sdmshrike-mtp.dtsi"
/ {
model = "MTP";
compatible = "qcom,sdmshrike-mtp", "qcom,sdmshrike", "qcom,mtp";
qcom,board-id = <8 0>;
};

22
arch/arm64/boot/dts/qcom/sdmshrike.dts Normal file
View File

@ -0,0 +1,22 @@
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "sdmshrike.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SDMSHRIKE SoC";
compatible = "qcom,sdmshrike";
qcom,pmic-name = "PM855";
qcom,board-id = <0 0>;
};

193
arch/arm64/boot/dts/qcom/sdmshrike.dtsi
View File

@ -25,7 +25,8 @@
/ {
model = "Qualcomm Technologies, Inc. SDMSHRIKE";
compatible = "qcom,sdmshrike";
qcom,msm-id = <340 0x0>;
qcom,msm-name = "SDMSHRIKE";
qcom,msm-id = <340 0x10000>;
interrupt-parent = <&pdc>;
aliases {
@ -59,6 +60,16 @@
cache-level = <3>;
};
};
L1_I_0: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
L1_D_0: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
};
CPU1: cpu@100 {
@ -74,6 +85,16 @@
cache-level = <2>;
next-level-cache = <&L3_0>;
};
L1_I_100: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
L1_D_100: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
};
CPU2: cpu@200 {
@ -89,6 +110,16 @@
cache-level = <2>;
next-level-cache = <&L3_0>;
};
L1_I_200: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
L1_D_200: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
};
CPU3: cpu@300 {
@ -104,6 +135,16 @@
cache-level = <2>;
next-level-cache = <&L3_0>;
};
L1_I_300: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
L1_D_300: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0xa000>;
};
};
CPU4: cpu@400 {
@ -119,6 +160,16 @@
cache-level = <2>;
next-level-cache = <&L3_0>;
};
L1_I_400: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
L1_D_400: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
};
CPU5: cpu@500 {
@ -134,6 +185,16 @@
cache-level = <2>;
next-level-cache = <&L3_0>;
};
L1_I_500: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
L1_D_500: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
};
CPU6: cpu@600 {
@ -149,6 +210,16 @@
cache-level = <2>;
next-level-cache = <&L3_0>;
};
L1_I_600: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
L1_D_600: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
};
CPU7: cpu@700 {
@ -164,6 +235,16 @@
cache-level = <2>;
next-level-cache = <&L3_0>;
};
L1_I_700: l1-icache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
L1_D_700: l1-dcache {
compatible = "arm,arch-cache";
qcom,dump-size = <0x14000>;
};
};
cpu-map {
@ -210,6 +291,90 @@
};
};
cpuss_dump {
compatible = "qcom,cpuss-dump";
qcom,l1_i_cache0 {
qcom,dump-node = <&L1_I_0>;
qcom,dump-id = <0x60>;
};
qcom,l1_i_cache1 {
qcom,dump-node = <&L1_I_100>;
qcom,dump-id = <0x61>;
};
qcom,l1_i_cache2 {
qcom,dump-node = <&L1_I_200>;
qcom,dump-id = <0x62>;
};
qcom,l1_i_cache3 {
qcom,dump-node = <&L1_I_300>;
qcom,dump-id = <0x63>;
};
qcom,l1_i_cache100 {
qcom,dump-node = <&L1_I_400>;
qcom,dump-id = <0x64>;
};
qcom,l1_i_cache101 {
qcom,dump-node = <&L1_I_500>;
qcom,dump-id = <0x65>;
};
qcom,l1_i_cache102 {
qcom,dump-node = <&L1_I_600>;
qcom,dump-id = <0x66>;
};
qcom,l1_i_cache103 {
qcom,dump-node = <&L1_I_700>;
qcom,dump-id = <0x67>;
};
qcom,l1_d_cache0 {
qcom,dump-node = <&L1_D_0>;
qcom,dump-id = <0x80>;
};
qcom,l1_d_cache1 {
qcom,dump-node = <&L1_D_100>;
qcom,dump-id = <0x81>;
};
qcom,l1_d_cache2 {
qcom,dump-node = <&L1_D_200>;
qcom,dump-id = <0x82>;
};
qcom,l1_d_cache3 {
qcom,dump-node = <&L1_D_300>;
qcom,dump-id = <0x83>;
};
qcom,l1_d_cache100 {
qcom,dump-node = <&L1_D_400>;
qcom,dump-id = <0x84>;
};
qcom,l1_d_cache101 {
qcom,dump-node = <&L1_D_500>;
qcom,dump-id = <0x85>;
};
qcom,l1_d_cache102 {
qcom,dump-node = <&L1_D_600>;
qcom,dump-id = <0x86>;
};
qcom,l1_d_cache103 {
qcom,dump-node = <&L1_D_700>;
qcom,dump-id = <0x87>;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@ -492,6 +657,24 @@
};
};
qcom,chd_silver {
compatible = "qcom,core-hang-detect";
label = "silver";
qcom,threshold-arr = <0x18000058 0x18010058
0x18020058 0x18030058>;
qcom,config-arr = <0x18000060 0x18010060
0x18020060 0x18030060>;
};
qcom,chd_gold {
compatible = "qcom,core-hang-detect";
label = "gold";
qcom,threshold-arr = <0x18040058 0x18050058
0x18060058 0x18070058>;
qcom,config-arr = <0x18040060 0x18050060
0x18060060 0x18070060>;
};
qcom,llcc@9200000 {
compatible = "qcom,llcc-core", "syscon", "simple-mfd";
reg = <0x9200000 0x450000>;
@ -899,11 +1082,11 @@
memory-region = <&pil_adsp_mem>;
/* Inputs from lpass */
interrupts-extended = <&intc 0 162 1>,
interrupts-extended = <&pdc 0 162 1>,
<&adsp_smp2p_in 0 0>,
<&adsp_smp2p_in 2 0>,
<&adsp_smp2p_in 1 0>,
<&adsp_smp2p_in 3 0>,
<&adsp_smp2p_in 0 0>;
<&adsp_smp2p_in 3 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
@ -911,7 +1094,7 @@
"qcom,err-ready",
"qcom,stop-ack";
/* Outputs from lpass */
/* Outputs to lpass */
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
};

2
arch/arm64/configs/sdmshrike-perf_defconfig
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@ -257,6 +257,8 @@ CONFIG_SLIMBUS_MSM_NGD=y
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
CONFIG_PINCTRL_SDMSHRIKE=y
CONFIG_GPIO_SYSFS=y
CONFIG_POWER_RESET_QCOM=y
CONFIG_QCOM_DLOAD_MODE=y
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_THERMAL=y

2
arch/arm64/configs/sdmshrike_defconfig
View File

@ -267,6 +267,8 @@ CONFIG_SLIMBUS_MSM_NGD=y
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
CONFIG_PINCTRL_SDMSHRIKE=y
CONFIG_GPIO_SYSFS=y
CONFIG_POWER_RESET_QCOM=y
CONFIG_QCOM_DLOAD_MODE=y
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_THERMAL=y