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[TG3]: Fix SRAM access during tg3_init_one()

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5700 and 5701 will not return correct SRAM data when the chip is in
D3hot power state. tg3_get_eeprom_hw_cfg() must first put the device
in D0 before reading SRAM.

Thanks to Thomas Chenault at Dell for noticing this problem.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan 2006-03-22 01:05:31 -08:00 committed by David S. Miller
parent 9a6b9f2e76
commit caf636c760
1 changed files with 9 additions and 3 deletions
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12
drivers/net/tg3.c
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@ -9436,12 +9436,18 @@ static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
return NULL; return NULL;
} }
/* Since this function may be called in D3-hot power state during
* tg3_init_one(), only config cycles are allowed.
*/
static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
{ {
u32 val; u32 val;
u16 pmcsr;
/* On some early chips the SRAM cannot be accessed in D3hot state,
* so need make sure we're in D0.
*/
pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
msleep(1);
/* Make sure register accesses (indirect or otherwise) /* Make sure register accesses (indirect or otherwise)
* will function correctly. * will function correctly.