mirror of
https://github.com/rd-stuffs/msm-4.14.git
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Staging: sxg: Indentation fixes - mostly 80 char lines
Fix up the indentation to Linux style. There was some indentation which was not as per Linux style specially related to 80 char lines. Signed-off-by: LinSysSoft Sahara Team <saharaproj@linsyssoft.com> Signed-off-by: Christopher Harrer <charrer@alacritech.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Mithlesh Thukral
Greg Kroah-Hartman
parent
ddd6f0a8c9
commit
cb636fe382
File diff suppressed because it is too large
Load Diff
@ -161,7 +161,8 @@ struct sxg_stats {
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* If we fill up our array of packet pointers, then indicate this
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* block up now and start on a new one.
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*/
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#define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, _NumPackets) { \
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#define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, \
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_NumPackets) { \
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(_IndicationList)[_NumPackets] = (_Packet); \
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(_NumPackets)++; \
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if((_NumPackets) == SXG_RCV_ARRAYSIZE) { \
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@ -182,13 +183,16 @@ struct sxg_stats {
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}
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#define SXG_REINIATIALIZE_PACKET(_Packet) \
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{} /*_NdisReinitializePacket(_Packet)*/ /* this is not necessary with an skb */
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{} /*_NdisReinitializePacket(_Packet)*/
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/* this is not necessary with an skb */
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/* Definitions to initialize Dumb-nic Receive NBLs */
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#define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((struct sxg_rcv_nbl_reserved *)((_Packet)->MiniportReservedEx))->RcvDataBufferHdr)
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#define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((struct sxg_rcv_nbl_reserved *)\
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((_Packet)->MiniportReservedEx))->RcvDataBufferHdr)
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#define SXG_RCV_SET_CHECKSUM_INFO(_Packet, _Cpi) \
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NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), TcpIpChecksumPacketInfo) = (PVOID)(_Cpi)
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NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), \
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TcpIpChecksumPacketInfo) = (PVOID)(_Cpi)
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#define SXG_RCV_SET_TOEPLITZ(_Packet, _Toeplitz, _Type, _Function) { \
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NDIS_PACKET_SET_HASH_VALUE((_Packet), (_Toeplitz)); \
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@ -222,7 +226,8 @@ struct sxg_stats {
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if((_pAdapt)->FreeRcvBufferCount) { \
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ASSERT(!(IsListEmpty(&(_pAdapt)->FreeRcvBuffers))); \
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_ple = RemoveHeadList(&(_pAdapt)->FreeRcvBuffers); \
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(_Hdr) = container_of(_ple, struct sxg_rcv_data_buffer_hdr, FreeList); \
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(_Hdr) = container_of(_ple, struct sxg_rcv_data_buffer_hdr, \
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FreeList); \
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(_pAdapt)->FreeRcvBufferCount--; \
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ASSERT((_Hdr)->State == SXG_BUFFER_FREE); \
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} \
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@ -234,7 +239,8 @@ struct sxg_stats {
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(_Hdr)->State, (_Hdr)->VirtualAddress); \
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/* SXG_RESTORE_MDL_OFFSET(_Hdr); */ \
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(_pAdapt)->FreeRcvBufferCount++; \
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ASSERT(((_pAdapt)->AllRcvBlockCount * SXG_RCV_DESCRIPTORS_PER_BLOCK) >= (_pAdapt)->FreeRcvBufferCount); \
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ASSERT(((_pAdapt)->AllRcvBlockCount * SXG_RCV_DESCRIPTORS_PER_BLOCK) \
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>= (_pAdapt)->FreeRcvBufferCount); \
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ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
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(_Hdr)->State = SXG_BUFFER_FREE; \
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InsertTailList(&(_pAdapt)->FreeRcvBuffers, &((_Hdr)->FreeList)); \
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@ -252,7 +258,7 @@ struct sxg_stats {
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#define SXG_FREE_SGL_BUFFER(_pAdapt, _Sgl, _NB) { \
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spin_lock(&(_pAdapt)->SglQLock); \
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(_pAdapt)->FreeSglBufferCount++; \
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ASSERT((_pAdapt)->AllSglBufferCount >= (_pAdapt)->FreeSglBufferCount);\
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ASSERT((_pAdapt)->AllSglBufferCount >= (_pAdapt)->FreeSglBufferCount); \
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ASSERT(!((_Sgl)->State & SXG_BUFFER_FREE)); \
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(_Sgl)->State = SXG_BUFFER_FREE; \
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InsertTailList(&(_pAdapt)->FreeSglBuffers, &(_Sgl)->FreeList); \
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@ -280,7 +286,8 @@ struct sxg_stats {
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if((_pAdapt)->FreeSglBufferCount) { \
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ASSERT(!(IsListEmpty(&(_pAdapt)->FreeSglBuffers))); \
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_ple = RemoveHeadList(&(_pAdapt)->FreeSglBuffers); \
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(_Sgl) = container_of(_ple, struct sxg_scatter_gather, FreeList); \
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(_Sgl) = container_of(_ple, struct sxg_scatter_gather, \
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FreeList); \
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(_pAdapt)->FreeSglBufferCount--; \
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ASSERT((_Sgl)->State == SXG_BUFFER_FREE); \
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(_Sgl)->State = SXG_BUFFER_BUSY; \
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@ -378,7 +385,8 @@ enum SXG_UCODE_SEL {
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/* This probably lives in a proto.h file. Move later */
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#define SXG_MULTICAST_PACKET(_pether) ((_pether)->ether_dhost[0] & 0x01)
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#define SXG_BROADCAST_PACKET(_pether) ((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) && \
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#define SXG_BROADCAST_PACKET(_pether) \
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((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) && \
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(*(u16 *)&(_pether)->ether_dhost[4] == 0xFFFF))
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/* For DbgPrints */
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@ -475,7 +483,8 @@ struct mcast_address {
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#define MAC_ALLMCAST 0x00000020
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#define SLIC_DUPLEX(x) ((x==LINK_FULLD) ? "FDX" : "HDX")
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#define SLIC_SPEED(x) ((x==LINK_100MB) ? "100Mb" : ((x==LINK_1000MB) ? "1000Mb" : " 10Mb"))
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#define SLIC_SPEED(x) ((x==LINK_100MB) ? "100Mb" : \
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((x==LINK_1000MB) ? "1000Mb" : " 10Mb"))
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#define SLIC_LINKSTATE(x) ((x==LINK_DOWN) ? "Down" : "Up ")
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#define SLIC_ADAPTER_STATE(x) ((x==ADAPT_UP) ? "UP" : "Down")
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#define SLIC_CARD_STATE(x) ((x==CARD_UP) ? "UP" : "Down")
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@ -687,7 +696,6 @@ struct adapter_t {
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/* PSXG_DUMP_CMD DumpBuffer; */ /* 68k - Cmd and Buffer */
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/* dma_addr_t PDumpBuffer; */ /* Physical address */
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/*#endif */ /* SXG_FAILURE_DUMP */
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};
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#if SLIC_DUMP_ENABLED
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@ -735,7 +743,8 @@ struct slic_crash_info {
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#if defined(CONFIG_X86_64) || defined(CONFIG_IA64)
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#define SXG_GET_ADDR_LOW(_addr) (u32)((u64)(_addr) & 0x00000000FFFFFFFF)
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#define SXG_GET_ADDR_HIGH(_addr) (u32)(((u64)(_addr) >> 32) & 0x00000000FFFFFFFF)
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#define SXG_GET_ADDR_HIGH(_addr) \
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(u32)(((u64)(_addr) >> 32) & 0x00000000FFFFFFFF)
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#else
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#define SXG_GET_ADDR_LOW(_addr) (u32)_addr
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#define SXG_GET_ADDR_HIGH(_addr) (u32)0
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@ -744,8 +753,8 @@ struct slic_crash_info {
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#define FLUSH TRUE
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#define DONT_FLUSH FALSE
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#define SIOCSLICDUMPCARD SIOCDEVPRIVATE+9
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#define SIOCSLICSETINTAGG SIOCDEVPRIVATE+10
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#define SIOCSLICTRACEDUMP SIOCDEVPRIVATE+11
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#define SIOCSLICDUMPCARD (SIOCDEVPRIVATE+9)
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#define SIOCSLICSETINTAGG (SIOCDEVPRIVATE+10)
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#define SIOCSLICTRACEDUMP (SIOCDEVPRIVATE+11)
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#endif /* __SXG_DRIVER_H__ */
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@ -68,7 +68,7 @@ struct list_entry {
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/* These two have to be inlined since they return things. */
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static __inline struct list_entry *RemoveHeadList(struct list_entry *l)
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static inline struct list_entry *RemoveHeadList(struct list_entry *l)
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{
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struct list_entry *f;
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struct list_entry *e;
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@ -81,7 +81,7 @@ static __inline struct list_entry *RemoveHeadList(struct list_entry *l)
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return (e);
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}
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static __inline struct list_entry *RemoveTailList(struct list_entry *l)
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static inline struct list_entry *RemoveTailList(struct list_entry *l)
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{
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struct list_entry *b;
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struct list_entry *e;
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@ -140,8 +140,10 @@ static __inline struct list_entry *RemoveTailList(struct list_entry *l)
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#define SXG_TIMESTAMP(value)
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#endif
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#define WRITE_REG(reg,value,flush) sxg_reg32_write((®), (value), (flush))
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#define WRITE_REG64(a,reg,value,cpu) sxg_reg64_write((a),(®),(value),(cpu))
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#define WRITE_REG(reg,value,flush) \
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sxg_reg32_write((®), (value), (flush))
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#define WRITE_REG64(a,reg,value,cpu) \
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sxg_reg64_write((a),(®),(value),(cpu))
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#define READ_REG(reg,value) (value) = readl((void __iomem *)(®))
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#endif /* _SLIC_OS_SPECIFIC_H_ */
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@ -58,7 +58,7 @@
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#define ASSERT(a) \
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{ \
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if (!(a)) { \
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DBG_ERROR("ASSERT() Failure: file %s, function %s line %d\n",\
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DBG_ERROR("ASSERT() Failure: file %s, function %s line %d\n", \
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__FILE__, __func__, __LINE__); \
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} \
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}
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@ -88,12 +88,13 @@ extern ulong ATKTimerDiv;
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* parameters.
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*/
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struct trace_entry {
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char name[8]; /* 8 character name - like 's'i'm'b'a'r'c'v' */
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char name[8];/* 8 character name - like 's'i'm'b'a'r'c'v' */
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u32 time; /* Current clock tic */
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unsigned char cpu; /* Current CPU */
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unsigned char irql; /* Current IRQL */
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unsigned char driver; /* The driver which added the trace call */
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unsigned char pad2; /* pad to 4 byte boundary - will probably get used */
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unsigned char driver;/* The driver which added the trace call */
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/* pad to 4 byte boundary - will probably get used */
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unsigned char pad2;
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u32 arg1; /* Caller arg1 */
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u32 arg2; /* Caller arg2 */
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u32 arg3; /* Caller arg3 */
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@ -108,7 +109,8 @@ struct trace_entry {
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#define TRACE_ENTRIES 1024
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struct sxg_trace_buffer {
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unsigned int size; /* aid for windbg extension */
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/* aid for windbg extension */
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unsigned int size;
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unsigned int in; /* Where to add */
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unsigned int level; /* Current Trace level */
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spinlock_t lock; /* For MP tracing */
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@ -144,7 +146,7 @@ struct sxg_trace_buffer {
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#if ATK_TRACE_ENABLED
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#define SXG_TRACE(tdriver, buffer, tlevel, tname, a1, a2, a3, a4) { \
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if ((buffer) && ((buffer)->level >= (tlevel))) { \
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unsigned int trace_irql = 0; /* ?????? FIX THIS */ \
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unsigned int trace_irql = 0;/* ?????? FIX THIS */\
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unsigned int trace_len; \
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struct trace_entry *trace_entry; \
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struct timeval timev; \
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@ -158,7 +160,7 @@ struct sxg_trace_buffer {
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trace_len = trace_len > 8 ? 8 : trace_len; \
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memcpy(trace_entry->name, (tname), trace_len); \
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trace_entry->time = timev.tv_usec; \
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trace_entry->cpu = (unsigned char)(smp_processor_id() & 0xFF); \
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trace_entry->cpu = (unsigned char)(smp_processor_id() & 0xFF);\
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trace_entry->driver = (tdriver); \
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trace_entry->irql = trace_irql; \
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trace_entry->arg1 = (ulong)(a1); \
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@ -129,7 +129,7 @@ struct sxg_ucode_regs {
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* base. As extended codes are added, reduce the first array value in
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* the following field
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*/
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u32 PadToNextCpu[94][16]; /* 94 = 128 - 34 (34 = Excodes 0 - 33) */
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u32 PadToNextCpu[94][16]; /* 94 = 128 - 34 (34 = Excodes 0 - 33)*/
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};
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/* Interrupt control register (0) values */
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@ -145,7 +145,8 @@ struct sxg_ucode_regs {
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#define SXG_MIN_AGG_DEFAULT 0x0010 /* Minimum aggregation default */
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#define SXG_MAX_AGG_DEFAULT 0x0040 /* Maximum aggregation default */
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#define SXG_MAX_AGG_SHIFT 16 /* Maximum in top 16 bits of register */
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#define SXG_AGG_XMT_DISABLE 0x80000000 /* Disable interrupt aggregation on xmt */
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/* Disable interrupt aggregation on xmt */
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#define SXG_AGG_XMT_DISABLE 0x80000000
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/* The Microcode supports up to 8 RSS queues */
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#define SXG_MAX_RSS 8
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@ -226,7 +227,7 @@ struct sxg_tcb_regs {
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#define SXG_ISR_ERR 0x80000000 /* Error */
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#define SXG_ISR_EVENT 0x40000000 /* Event ring event */
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#define SXG_ISR_NONE1 0x20000000 /* Not used */
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#define SXG_ISR_UPC 0x10000000 /* Dump/debug command complete */
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#define SXG_ISR_UPC 0x10000000 /* Dump/debug command complete*/
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#define SXG_ISR_LINK 0x08000000 /* Link event */
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#define SXG_ISR_PDQF 0x04000000 /* Processed data queue full */
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#define SXG_ISR_RMISS 0x02000000 /* Drop - no host buf */
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@ -335,7 +336,8 @@ struct sxg_event {
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*/
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#define EVENT_RING_SIZE 4096
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#define EVENT_RING_BATCH 16 /* Hand entries back 16 at a time. */
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#define EVENT_BATCH_LIMIT 256 /* Stop processing events after 4096 (256 * 16) */
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/* Stop processing events after 4096 (256 * 16) */
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#define EVENT_BATCH_LIMIT 256
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struct sxg_event_ring {
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struct sxg_event Ring[EVENT_RING_SIZE];
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@ -366,20 +368,20 @@ struct sxg_event_ring {
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#define SXG_LOCATE_TCP_FRAME_HDR(_TcpObject, _IPv6) \
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(((_TcpObject)->VlanId) ? \
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((_IPv6) ? /* Vlan frame header = yes */ \
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&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.SxgTcp : \
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&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.SxgTcp) : \
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&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.SxgTcp: \
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&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.SxgTcp): \
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((_IPv6) ? /* Vlan frame header = No */ \
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&(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.SxgTcp : \
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&(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp.SxgTcp))
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#define SXG_LOCATE_IP_FRAME_HDR(_TcpObject) \
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(_TcpObject)->VlanId ? \
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&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.Ip : \
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&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp.Ip: \
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&(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp.Ip
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#define SXG_LOCATE_IP6_FRAME_HDR(_TcpObject) \
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#define SXG_LOCATE_IP6_FRAME_HDR(TcpObject) \
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(_TcpObject)->VlanId ? \
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&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.Ip : \
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&(_TcpObject)->CompBuffer->Frame.HasVlan.TcpIp6.Ip: \
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&(_TcpObject)->CompBuffer->Frame.NoVlan.TcpIp6.Ip
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#if DBG
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@ -393,12 +395,14 @@ struct sxg_event_ring {
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*/
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#define SXG_DBG_HOP_LIMIT(_TcpObject, _FastPath) { \
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PIPV6_HDR _Ip6FrameHdr; \
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if((_TcpObject)->IPv6) { \
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if ((_TcpObject)->IPv6) { \
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_Ip6FrameHdr = SXG_LOCATE_IP6_FRAME_HDR((_TcpObject)); \
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if(_FastPath) { \
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_Ip6FrameHdr->HopLimit = (_TcpObject)->Cached.TtlOrHopLimit - 2; \
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if (_FastPath) { \
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_Ip6FrameHdr->HopLimit = \
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(_TcpObject)->Cached.TtlOrHopLimit - 2; \
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} else { \
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_Ip6FrameHdr->HopLimit = (_TcpObject)->Cached.TtlOrHopLimit - 1; \
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_Ip6FrameHdr->HopLimit = \
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(_TcpObject)->Cached.TtlOrHopLimit - 1; \
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} \
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} \
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}
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@ -415,7 +419,8 @@ struct sxg_event_ring {
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/* Structure and macros to manage a ring */
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struct sxg_ring_info {
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unsigned char Head; /* Where we add entries - Note unsigned char:RING_SIZE */
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/* Where we add entries - Note unsigned char:RING_SIZE */
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unsigned char Head;
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unsigned char Tail; /* Where we pull off completed entries */
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ushort Size; /* Ring size - Must be multiple of 2 */
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void * Context[SXG_MAX_RING_SIZE]; /* Shadow ring */
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@ -426,11 +431,16 @@ struct sxg_ring_info {
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(_ring).Tail = 0; \
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(_ring).Size = (_size); \
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}
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#define SXG_ADVANCE_INDEX(_index, _size) ((_index) = ((_index) + 1) & ((_size) - 1))
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#define SXG_PREVIOUS_INDEX(_index, _size) (((_index) - 1) &((_size) - 1))
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#define SXG_ADVANCE_INDEX(_index, _size) \
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((_index) = ((_index) + 1) & ((_size) - 1))
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#define SXG_PREVIOUS_INDEX(_index, _size) \
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(((_index) - 1) &((_size) - 1))
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#define SXG_RING_EMPTY(_ring) ((_ring)->Head == (_ring)->Tail)
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#define SXG_RING_FULL(_ring) ((((_ring)->Head + 1) & ((_ring)->Size - 1)) == (_ring)->Tail)
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#define SXG_RING_ADVANCE_HEAD(_ring) SXG_ADVANCE_INDEX((_ring)->Head, ((_ring)->Size))
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#define SXG_RING_FULL(_ring) \
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((((_ring)->Head + 1) & ((_ring)->Size - 1)) == (_ring)->Tail)
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#define SXG_RING_ADVANCE_HEAD(_ring) \
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SXG_ADVANCE_INDEX((_ring)->Head, ((_ring)->Size))
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#define SXG_RING_RETREAT_HEAD(_ring) ((_ring)->Head = \
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SXG_PREVIOUS_INDEX((_ring)->Head, (_ring)->Size))
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#define SXG_RING_ADVANCE_TAIL(_ring) { \
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@ -507,7 +517,8 @@ struct sxg_cmd {
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union {
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u32 Rsvd1; /* TOE NA */
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u32 SgeOffset; /* Slowpath - 2nd SGE offset */
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u32 Resid; /* MDL completion - clobbers update */
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/* MDL completion - clobbers update */
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u32 Resid;
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};
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union {
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u32 TotalLength; /* Total transfer length */
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@ -639,10 +650,10 @@ enum sxg_buffer_type {
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* Further complicating matters is the fact that the receive
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* buffers must be variable in length in order to accomodate
|
||||
* jumbo frame configurations. We configure the buffer
|
||||
* length so that the buffer and it's corresponding struct sxg_rcv_data_buffer_hdr
|
||||
* structure add up to an even boundary. Then we place the
|
||||
* remaining data structures after 128 of them as shown in
|
||||
* the following diagram:
|
||||
* length so that the buffer and it's corresponding struct
|
||||
* sxg_rcv_data_buffer_hdr structure add up to an even
|
||||
* boundary. Then we place the remaining data structures after 128
|
||||
* of them as shown in the following diagram:
|
||||
*
|
||||
* _________________________________________
|
||||
* | |
|
||||
@ -683,7 +694,8 @@ enum sxg_buffer_type {
|
||||
*/
|
||||
#define SXG_RCV_DATA_BUFFERS 8192 /* Amount to give to the card */
|
||||
#define SXG_INITIAL_RCV_DATA_BUFFERS 16384 /* Initial pool of buffers */
|
||||
#define SXG_MIN_RCV_DATA_BUFFERS 4096 /* Minimum amount and when to get more */
|
||||
/* Minimum amount and when to get more */
|
||||
#define SXG_MIN_RCV_DATA_BUFFERS 4096
|
||||
#define SXG_MAX_RCV_BLOCKS 256 /* = 32k receive buffers */
|
||||
|
||||
/* Receive buffer header */
|
||||
@ -699,7 +711,7 @@ struct sxg_rcv_data_buffer_hdr {
|
||||
struct list_entry FreeList; /* Free queue of buffers */
|
||||
unsigned char State; /* See SXG_BUFFER state above */
|
||||
unsigned char Status; /* Event status (to log PUSH) */
|
||||
struct sk_buff * skb; /* Double mapped (nbl and pkt) */
|
||||
struct sk_buff * skb; /* Double mapped (nbl and pkt)*/
|
||||
};
|
||||
|
||||
/*
|
||||
@ -708,15 +720,17 @@ struct sxg_rcv_data_buffer_hdr {
|
||||
*/
|
||||
#define SxgDumbRcvPacket skb
|
||||
|
||||
#define SXG_RCV_DATA_HDR_SIZE 256 /* Space for struct sxg_rcv_data_buffer_hdr */
|
||||
#define SXG_RCV_DATA_BUFFER_SIZE 2048 /* Non jumbo = 2k including HDR */
|
||||
/* Space for struct sxg_rcv_data_buffer_hdr */
|
||||
#define SXG_RCV_DATA_HDR_SIZE 256
|
||||
/* Non jumbo = 2k including HDR */
|
||||
#define SXG_RCV_DATA_BUFFER_SIZE 2048
|
||||
#define SXG_RCV_JUMBO_BUFFER_SIZE 10240 /* jumbo = 10k including HDR */
|
||||
|
||||
/* Receive data descriptor */
|
||||
struct sxg_rcv_data_descriptor {
|
||||
union {
|
||||
struct sk_buff *VirtualAddress; /* Host handle */
|
||||
u64 ForceTo8Bytes; /* Force x86 to 8-byte boundary */
|
||||
u64 ForceTo8Bytes; /*Force x86 to 8-byte boundary*/
|
||||
};
|
||||
dma_addr_t PhysicalAddress;
|
||||
};
|
||||
@ -733,15 +747,15 @@ struct sxg_rcv_descriptor_block {
|
||||
struct sxg_rcv_descriptor_block_hdr {
|
||||
void *VirtualAddress; /* start of 2k buffer */
|
||||
dma_addr_t PhysicalAddress; /* ..and it's physical address */
|
||||
struct list_entry FreeList; /* free queue of descriptor blocks */
|
||||
struct list_entry FreeList;/* free queue of descriptor blocks */
|
||||
unsigned char State; /* see sxg_buffer state above */
|
||||
};
|
||||
|
||||
/* Receive block header */
|
||||
struct sxg_rcv_block_hdr {
|
||||
void *VirtualAddress; /* Start of virtual memory */
|
||||
dma_addr_t PhysicalAddress; /* ..and it's physical address */
|
||||
struct list_entry AllList; /* Queue of all SXG_RCV_BLOCKS */
|
||||
dma_addr_t PhysicalAddress; /* ..and it's physical address*/
|
||||
struct list_entry AllList; /* Queue of all SXG_RCV_BLOCKS*/
|
||||
};
|
||||
|
||||
/* Macros to determine data structure offsets into receive block */
|
||||
@ -766,12 +780,13 @@ struct sxg_rcv_block_hdr {
|
||||
|
||||
/* Scatter gather list buffer */
|
||||
#define SXG_INITIAL_SGL_BUFFERS 8192 /* Initial pool of SGL buffers */
|
||||
#define SXG_MIN_SGL_BUFFERS 2048 /* Minimum amount and when to get more */
|
||||
#define SXG_MAX_SGL_BUFFERS 16384 /* Maximum to allocate (note ADAPT:ushort) */
|
||||
#define SXG_MIN_SGL_BUFFERS 2048 /* Minimum amount and when to get more*/
|
||||
/* Maximum to allocate (note ADAPT:ushort) */
|
||||
#define SXG_MAX_SGL_BUFFERS 16384
|
||||
|
||||
/*
|
||||
* SXG_SGL_POOL_PROPERTIES - This structure is used to define a pool of SGL buffers.
|
||||
* These buffers are allocated out of shared memory and used to
|
||||
* SXG_SGL_POOL_PROPERTIES - This structure is used to define a pool of SGL
|
||||
* buffers. These buffers are allocated out of shared memory and used to
|
||||
* contain a physical scatter gather list structure that is shared
|
||||
* with the card.
|
||||
*
|
||||
@ -801,29 +816,28 @@ struct sxg_sgl_pool_properties {
|
||||
|
||||
/*
|
||||
* At the moment I'm going to statically initialize 4 pools:
|
||||
* 100k buffer pool: The vast majority of the expected buffers are expected to
|
||||
* be less than or equal to 100k. At 30 entries per and
|
||||
* 100k buffer pool: The vast majority of the expected buffers are expected
|
||||
* to be less than or equal to 100k. At 30 entries per and
|
||||
* 8k initial buffers amounts to ~4MB of memory
|
||||
* NOTE - This used to be 64K with 20 entries, but during
|
||||
* WHQL NDIS 6.0 Testing (2c_mini6stress) MS does their
|
||||
* best to send absurd NBL's with ridiculous SGLs, we
|
||||
* have received 400byte sends contained in SGL's that
|
||||
* have 28 entries
|
||||
* 1M buffer pool: Buffers between 64k and 1M. Allocate 256 initial buffers
|
||||
* with 300 entries each => ~2MB of memory
|
||||
* 1M buffer pool: Buffers between 64k and 1M. Allocate 256 initial
|
||||
* buffers with 300 entries each => ~2MB of memory
|
||||
* 5M buffer pool: Not expected often, if at all. 32 initial buffers
|
||||
* at 1500 entries each => ~1MB of memory
|
||||
* 10M buffer pool: Not expected at all, except under pathelogical conditions.
|
||||
* Allocate one at initialization time.
|
||||
* Note - 10M is the current limit of what we can
|
||||
* realistically support due to the sahara SGL
|
||||
* bug described in the SAHARA SGL WORKAROUND below
|
||||
*
|
||||
* We will likely adjust the number of pools and/or pool properties over time..
|
||||
* Note - 10M is the current limit of what we can realistically
|
||||
* support due to the sahara SGL bug described in the
|
||||
* SAHARA SGL WORKAROUND below. We will likely adjust the
|
||||
* number of pools and/or pool properties over time.
|
||||
*/
|
||||
#define SXG_NUM_SGL_POOLS 4
|
||||
#define INITIALIZE_SGL_POOL_PROPERTIES \
|
||||
struct sxg_sgl_pool_properties SxgSglPoolProperties[SXG_NUM_SGL_POOLS] = \
|
||||
struct sxg_sgl_pool_properties SxgSglPoolProperties[SXG_NUM_SGL_POOLS] =\
|
||||
{ \
|
||||
{ 102400, 30, 8192, 2048, 16384, 256}, \
|
||||
{ 1048576, 300, 256, 128, 1024, 16}, \
|
||||
@ -858,17 +872,19 @@ extern struct sxg_sgl_pool_properties SxgSglPoolProperties[];
|
||||
* struct sxg_sgl_block_hdr, plus one for padding
|
||||
*/
|
||||
#define SXG_SGL_BLOCK_SIZE 65536
|
||||
#define SXG_SGL_ALLOCATION_SIZE(_Pool) SXG_SGL_BLOCK_SIZE + SXG_SGL_SIZE(_Pool)
|
||||
#define SXG_SGL_ALLOCATION_SIZE(_Pool) \
|
||||
SXG_SGL_BLOCK_SIZE + SXG_SGL_SIZE(_Pool)
|
||||
|
||||
struct sxg_sgl_block_hdr {
|
||||
ushort Pool; /* Associated SGL pool */
|
||||
struct list_entry List; /* struct sxg_scatter_gather blocks */
|
||||
/* struct sxg_scatter_gather blocks */
|
||||
struct list_entry List;
|
||||
dma64_addr_t PhysicalAddress;/* physical address */
|
||||
};
|
||||
|
||||
/*
|
||||
* The following definition denotes the maximum block of memory that the
|
||||
* card can DMA to. It is specified in the call to NdisMRegisterScatterGatherDma.
|
||||
* card can DMA to.It is specified in the call to NdisMRegisterScatterGatherDma.
|
||||
* For now, use the same value as used in the Slic/Oasis driver, which
|
||||
* is 128M. That should cover any expected MDL that I can think of.
|
||||
*/
|
||||
@ -912,13 +928,16 @@ struct sxg_scatter_gather {
|
||||
ushort Pool; /* Associated SGL pool */
|
||||
ushort Entries; /* SGL total entries */
|
||||
void * adapter; /* Back pointer to adapter */
|
||||
struct list_entry FreeList; /* Free struct sxg_scatter_gather blocks */
|
||||
struct list_entry AllList; /* All struct sxg_scatter_gather blocks */
|
||||
/* Free struct sxg_scatter_gather blocks */
|
||||
struct list_entry FreeList;
|
||||
/* All struct sxg_scatter_gather blocks */
|
||||
struct list_entry AllList;
|
||||
dma_addr_t PhysicalAddress;/* physical address */
|
||||
unsigned char State; /* See SXG_BUFFER state above */
|
||||
unsigned char CmdIndex; /* Command ring index */
|
||||
struct sk_buff *DumbPacket; /* Associated Packet */
|
||||
u32 Direction; /* For asynchronous completions */
|
||||
/* For asynchronous completions */
|
||||
u32 Direction;
|
||||
u32 CurOffset; /* Current SGL offset */
|
||||
u32 SglRef; /* SGL reference count */
|
||||
struct vlan_hdr VlanTag; /* VLAN tag to be inserted into SGL */
|
||||
@ -926,7 +945,10 @@ struct sxg_scatter_gather {
|
||||
struct sxg_x64_sgl Sgl; /* SGL handed to card */
|
||||
};
|
||||
|
||||
/* Note - the "- 1" is because struct sxg_scatter_gather=>struct sxg_x64_sgl includes 1 SGE.. */
|
||||
/*
|
||||
* Note - the "- 1" is because struct sxg_scatter_gather=>struct sxg_x64_sgl
|
||||
* includes 1 SGE..
|
||||
*/
|
||||
#define SXG_SGL_SIZE(_Pool) \
|
||||
(sizeof(struct sxg_scatter_gather) + \
|
||||
((SxgSglPoolProperties[_Pool].SGEntries - 1) * \
|
||||
@ -934,7 +956,8 @@ struct sxg_scatter_gather {
|
||||
|
||||
#if defined(CONFIG_X86_64)
|
||||
#define SXG_SGL_BUFFER(_SxgSgl) (&_SxgSgl->Sgl)
|
||||
#define SXG_SGL_BUFFER_LENGTH(_SxgSgl) ((_SxgSgl)->Entries * sizeof(struct sxg_x64_sge))
|
||||
#define SXG_SGL_BUFFER_LENGTH(_SxgSgl) ((_SxgSgl)->Entries * \
|
||||
sizeof(struct sxg_x64_sge))
|
||||
#define SXG_SGL_BUF_SIZE sizeof(struct sxg_x64_sgl)
|
||||
#elif defined(CONFIG_X86)
|
||||
/* Force NDIS to give us it's own buffer so we can reformat to our own */
|
||||
@ -952,7 +975,8 @@ struct sxg_ucode_stats {
|
||||
u32 ERDrops; /* Rcv drops due to ER full */
|
||||
u32 NBDrops; /* Rcv drops due to out of host buffers */
|
||||
u32 PQDrops; /* Rcv drops due to PDQ full */
|
||||
u32 BFDrops; /* Rcv drops due to bad frame: no link addr match, frlen > max */
|
||||
/* Rcv drops due to bad frame: no link addr match, frlen > max */
|
||||
u32 BFDrops;
|
||||
u32 UPDrops; /* Rcv drops due to UPFq full */
|
||||
u32 XNoBufs; /* Xmt drop due to no DRAM Xmit buffer or PxyBuf */
|
||||
};
|
||||
|
||||
@ -33,14 +33,18 @@
|
||||
#define SSID_FUNC_MASK 0xF000 /* Subsystem function mask */
|
||||
|
||||
/* Base SSID's */
|
||||
#define SSID_SAHARA_PROTO 0x0018 /* 100022 Sahara prototype (XenPak) board */
|
||||
/* 100022 Sahara prototype (XenPak) board */
|
||||
#define SSID_SAHARA_PROTO 0x0018
|
||||
#define SSID_SAHARA_FIBER 0x0019 /* 100023 Sahara 1-port fiber board */
|
||||
#define SSID_SAHARA_COPPER 0x001A /* 100024 Sahara 1-port copper board */
|
||||
|
||||
/* Useful SSID macros */
|
||||
#define SSID_BASE(ssid) ((ssid) & SSID_BASE_MASK) /* isolate base SSID bits */
|
||||
#define SSID_OEM(ssid) ((ssid) & SSID_OEM_MASK) /* isolate SSID OEM bits */
|
||||
#define SSID_FUNC(ssid) ((ssid) & SSID_FUNC_MASK) /* isolate SSID function bits */
|
||||
/* isolate base SSID bits */
|
||||
#define SSID_BASE(ssid) ((ssid) & SSID_BASE_MASK)
|
||||
/* isolate SSID OEM bits */
|
||||
#define SSID_OEM(ssid) ((ssid) & SSID_OEM_MASK)
|
||||
/* isolate SSID function bits */
|
||||
#define SSID_FUNC(ssid) ((ssid) & SSID_FUNC_MASK)
|
||||
|
||||
|
||||
/* HW Register Space */
|
||||
@ -119,11 +123,12 @@ struct sxg_hw_regs {
|
||||
#define MICROCODE_ADDRESS_GO 0x80000000 /* Start microcode */
|
||||
#define MICROCODE_ADDRESS_WRITE 0x40000000 /* Store microcode */
|
||||
#define MICROCODE_ADDRESS_READ 0x20000000 /* Read microcode */
|
||||
#define MICROCODE_ADDRESS_PARITY 0x10000000 /* Parity error detected */
|
||||
#define MICROCODE_ADDRESS_PARITY 0x10000000/* Parity error detected */
|
||||
#define MICROCODE_ADDRESS_MASK 0x00001FFF /* Address bits */
|
||||
|
||||
/* Link Address Registers */
|
||||
#define LINK_ADDRESS_ENABLE 0x80000000 /* Applied to link address high */
|
||||
/* Applied to link address high */
|
||||
#define LINK_ADDRESS_ENABLE 0x80000000
|
||||
|
||||
/* Microsoft register space size */
|
||||
#define SXG_UCODEREG_MEMSIZE 0x40000 /* 256k */
|
||||
@ -135,21 +140,28 @@ struct sxg_hw_regs {
|
||||
*/
|
||||
#define SXG_ADDRESS_CODE_SHIFT 2 /* Base command code */
|
||||
#define SXG_ADDRESS_CODE_MASK 0x0000003C
|
||||
#define SXG_ADDRESS_EXCODE_SHIFT 6 /* Extended (or sub) command code */
|
||||
/* Extended (or sub) command code */
|
||||
#define SXG_ADDRESS_EXCODE_SHIFT 6
|
||||
#define SXG_ADDRESS_EXCODE_MASK 0x00001FC0
|
||||
#define SXG_ADDRESS_CPUID_SHIFT 13 /* CPU */
|
||||
#define SXG_ADDRESS_CPUID_MASK 0x0003E000
|
||||
#define SXG_REGISTER_SIZE_PER_CPU 0x00002000 /* Used to sanity check UCODE_REGS structure */
|
||||
/* Used to sanity check UCODE_REGS structure */
|
||||
#define SXG_REGISTER_SIZE_PER_CPU 0x00002000
|
||||
|
||||
/* Sahara receive sequencer status values */
|
||||
#define SXG_RCV_STATUS_ATTN 0x80000000 /* Attention */
|
||||
#define SXG_RCV_STATUS_TRANSPORT_MASK 0x3F000000 /* Transport mask */
|
||||
#define SXG_RCV_STATUS_TRANSPORT_ERROR 0x20000000 /* Transport error */
|
||||
#define SXG_RCV_STATUS_TRANSPORT_CSUM 0x23000000 /* Transport cksum error */
|
||||
#define SXG_RCV_STATUS_TRANSPORT_UFLOW 0x22000000 /* Transport underflow */
|
||||
#define SXG_RCV_STATUS_TRANSPORT_HDRLEN 0x20000000 /* Transport header length */
|
||||
#define SXG_RCV_STATUS_TRANSPORT_FLAGS 0x10000000 /* Transport flags detected */
|
||||
#define SXG_RCV_STATUS_TRANSPORT_OPTS 0x08000000 /* Transport options detected */
|
||||
/* Transport cksum error */
|
||||
#define SXG_RCV_STATUS_TRANSPORT_CSUM 0x23000000
|
||||
/* Transport underflow */
|
||||
#define SXG_RCV_STATUS_TRANSPORT_UFLOW 0x22000000
|
||||
/* Transport header length */
|
||||
#define SXG_RCV_STATUS_TRANSPORT_HDRLEN 0x20000000
|
||||
/* Transport flags detected */
|
||||
#define SXG_RCV_STATUS_TRANSPORT_FLAGS 0x10000000
|
||||
/* Transport options detected */
|
||||
#define SXG_RCV_STATUS_TRANSPORT_OPTS 0x08000000
|
||||
#define SXG_RCV_STATUS_TRANSPORT_SESS_MASK 0x07000000 /* Transport DDP */
|
||||
#define SXG_RCV_STATUS_TRANSPORT_DDP 0x06000000 /* Transport DDP */
|
||||
#define SXG_RCV_STATUS_TRANSPORT_iSCSI 0x05000000 /* Transport iSCSI */
|
||||
@ -159,33 +171,53 @@ struct sxg_hw_regs {
|
||||
#define SXG_RCV_STATUS_TRANSPORT_SMB 0x01000000 /* Transport SMB */
|
||||
#define SXG_RCV_STATUS_NETWORK_MASK 0x00FF0000 /* Network mask */
|
||||
#define SXG_RCV_STATUS_NETWORK_ERROR 0x00800000 /* Network error */
|
||||
#define SXG_RCV_STATUS_NETWORK_CSUM 0x00830000 /* Network cksum error */
|
||||
#define SXG_RCV_STATUS_NETWORK_UFLOW 0x00820000 /* Network underflow error */
|
||||
#define SXG_RCV_STATUS_NETWORK_HDRLEN 0x00800000 /* Network header length */
|
||||
#define SXG_RCV_STATUS_NETWORK_OFLOW 0x00400000 /* Network overflow detected */
|
||||
#define SXG_RCV_STATUS_NETWORK_MCAST 0x00200000 /* Network multicast detected */
|
||||
#define SXG_RCV_STATUS_NETWORK_OPTIONS 0x00100000 /* Network options detected */
|
||||
#define SXG_RCV_STATUS_NETWORK_OFFSET 0x00080000 /* Network offset detected */
|
||||
#define SXG_RCV_STATUS_NETWORK_FRAGMENT 0x00040000 /* Network fragment detected */
|
||||
#define SXG_RCV_STATUS_NETWORK_TRANS_MASK 0x00030000 /* Network transport type mask */
|
||||
/* Network cksum error */
|
||||
#define SXG_RCV_STATUS_NETWORK_CSUM 0x00830000
|
||||
/* Network underflow error */
|
||||
#define SXG_RCV_STATUS_NETWORK_UFLOW 0x00820000
|
||||
/* Network header length */
|
||||
#define SXG_RCV_STATUS_NETWORK_HDRLEN 0x00800000
|
||||
/* Network overflow detected */
|
||||
#define SXG_RCV_STATUS_NETWORK_OFLOW 0x00400000
|
||||
/* Network multicast detected */
|
||||
#define SXG_RCV_STATUS_NETWORK_MCAST 0x00200000
|
||||
/* Network options detected */
|
||||
#define SXG_RCV_STATUS_NETWORK_OPTIONS 0x00100000
|
||||
/* Network offset detected */
|
||||
#define SXG_RCV_STATUS_NETWORK_OFFSET 0x00080000
|
||||
/* Network fragment detected */
|
||||
#define SXG_RCV_STATUS_NETWORK_FRAGMENT 0x00040000
|
||||
/* Network transport type mask */
|
||||
#define SXG_RCV_STATUS_NETWORK_TRANS_MASK 0x00030000
|
||||
#define SXG_RCV_STATUS_NETWORK_UDP 0x00020000 /* UDP */
|
||||
#define SXG_RCV_STATUS_NETWORK_TCP 0x00010000 /* TCP */
|
||||
#define SXG_RCV_STATUS_IPONLY 0x00008000 /* IP-only not TCP */
|
||||
#define SXG_RCV_STATUS_PKT_PRI 0x00006000 /* Receive priority */
|
||||
#define SXG_RCV_STATUS_PKT_PRI_SHFT 13 /* Receive priority shift */
|
||||
#define SXG_RCV_STATUS_PARITY 0x00001000 /* MAC Receive RAM parity error */
|
||||
#define SXG_RCV_STATUS_ADDRESS_MASK 0x00000F00 /* Link address detection mask */
|
||||
/* Receive priority */
|
||||
#define SXG_RCV_STATUS_PKT_PRI 0x00006000
|
||||
/* Receive priority shift */
|
||||
#define SXG_RCV_STATUS_PKT_PRI_SHFT 13
|
||||
/* MAC Receive RAM parity error */
|
||||
#define SXG_RCV_STATUS_PARITY 0x00001000
|
||||
/* Link address detection mask */
|
||||
#define SXG_RCV_STATUS_ADDRESS_MASK 0x00000F00
|
||||
|
||||
#define SXG_RCV_STATUS_ADDRESS_D 0x00000B00 /* Link address D */
|
||||
#define SXG_RCV_STATUS_ADDRESS_C 0x00000A00 /* Link address C */
|
||||
#define SXG_RCV_STATUS_ADDRESS_B 0x00000900 /* Link address B */
|
||||
#define SXG_RCV_STATUS_ADDRESS_A 0x00000800 /* Link address A */
|
||||
#define SXG_RCV_STATUS_ADDRESS_BCAST 0x00000300 /* Link address broadcast */
|
||||
#define SXG_RCV_STATUS_ADDRESS_MCAST 0x00000200 /* Link address multicast */
|
||||
#define SXG_RCV_STATUS_ADDRESS_CMCAST 0x00000100 /* Link control multicast */
|
||||
#define SXG_RCV_STATUS_LINK_MASK 0x000000FF /* Link status mask */
|
||||
/* Link address broadcast */
|
||||
#define SXG_RCV_STATUS_ADDRESS_BCAST 0x00000300
|
||||
/* Link address multicast */
|
||||
#define SXG_RCV_STATUS_ADDRESS_MCAST 0x00000200
|
||||
/* Link control multicast */
|
||||
#define SXG_RCV_STATUS_ADDRESS_CMCAST 0x00000100
|
||||
/* Link status mask */
|
||||
#define SXG_RCV_STATUS_LINK_MASK 0x000000FF
|
||||
#define SXG_RCV_STATUS_LINK_ERROR 0x00000080 /* Link error */
|
||||
#define SXG_RCV_STATUS_LINK_MASK 0x000000FF /* Link status mask */
|
||||
#define SXG_RCV_STATUS_LINK_PARITY 0x00000087 /* RcvMacQ parity error */
|
||||
/* Link status mask */
|
||||
#define SXG_RCV_STATUS_LINK_MASK 0x000000FF
|
||||
/* RcvMacQ parity error */
|
||||
#define SXG_RCV_STATUS_LINK_PARITY 0x00000087
|
||||
#define SXG_RCV_STATUS_LINK_EARLY 0x00000086 /* Data early */
|
||||
#define SXG_RCV_STATUS_LINK_BUFOFLOW 0x00000085 /* Buffer overflow */
|
||||
#define SXG_RCV_STATUS_LINK_CODE 0x00000084 /* Link code error */
|
||||
@ -196,21 +228,30 @@ struct sxg_hw_regs {
|
||||
#define SXG_RCV_STATUS_LINK_8023 0x00000020 /* 802.3 */
|
||||
#define SXG_RCV_STATUS_LINK_SNAP 0x00000010 /* Snap */
|
||||
#define SXG_RCV_STATUS_LINK_VLAN 0x00000008 /* VLAN */
|
||||
#define SXG_RCV_STATUS_LINK_TYPE_MASK 0x00000007 /* Network type mask */
|
||||
/* Network type mask */
|
||||
#define SXG_RCV_STATUS_LINK_TYPE_MASK 0x00000007
|
||||
#define SXG_RCV_STATUS_LINK_CONTROL 0x00000003 /* Control packet */
|
||||
#define SXG_RCV_STATUS_LINK_IPV6 0x00000002 /* IPv6 packet */
|
||||
#define SXG_RCV_STATUS_LINK_IPV4 0x00000001 /* IPv4 packet */
|
||||
|
||||
/* Sahara receive and transmit configuration registers */
|
||||
#define RCV_CONFIG_RESET 0x80000000 /* RcvConfig register reset */
|
||||
#define RCV_CONFIG_ENABLE 0x40000000 /* Enable the receive logic */
|
||||
#define RCV_CONFIG_ENPARSE 0x20000000 /* Enable the receive parser */
|
||||
#define RCV_CONFIG_SOCKET 0x10000000 /* Enable the socket detector */
|
||||
/* RcvConfig register reset */
|
||||
#define RCV_CONFIG_RESET 0x80000000
|
||||
/* Enable the receive logic */
|
||||
#define RCV_CONFIG_ENABLE 0x40000000
|
||||
/* Enable the receive parser */
|
||||
#define RCV_CONFIG_ENPARSE 0x20000000
|
||||
/* Enable the socket detector */
|
||||
#define RCV_CONFIG_SOCKET 0x10000000
|
||||
#define RCV_CONFIG_RCVBAD 0x08000000 /* Receive all bad frames */
|
||||
#define RCV_CONFIG_CONTROL 0x04000000 /* Receive all control frames */
|
||||
#define RCV_CONFIG_RCVPAUSE 0x02000000 /* Enable pause transmit when attn */
|
||||
#define RCV_CONFIG_TZIPV6 0x01000000 /* Include TCP port w/ IPv6 toeplitz */
|
||||
#define RCV_CONFIG_TZIPV4 0x00800000 /* Include TCP port w/ IPv4 toeplitz */
|
||||
/* Receive all control frames */
|
||||
#define RCV_CONFIG_CONTROL 0x04000000
|
||||
/* Enable pause transmit when attn */
|
||||
#define RCV_CONFIG_RCVPAUSE 0x02000000
|
||||
/* Include TCP port w/ IPv6 toeplitz */
|
||||
#define RCV_CONFIG_TZIPV6 0x01000000
|
||||
/* Include TCP port w/ IPv4 toeplitz */
|
||||
#define RCV_CONFIG_TZIPV4 0x00800000
|
||||
#define RCV_CONFIG_FLUSH 0x00400000 /* Flush buffers */
|
||||
#define RCV_CONFIG_PRIORITY_MASK 0x00300000 /* Priority level */
|
||||
#define RCV_CONFIG_CONN_MASK 0x000C0000 /* Number of connections */
|
||||
@ -223,20 +264,27 @@ struct sxg_hw_regs {
|
||||
#define RCV_CONFIG_HASH_16 0x00010000 /* Hash depth 16 */
|
||||
#define RCV_CONFIG_HASH_4 0x00020000 /* Hash depth 4 */
|
||||
#define RCV_CONFIG_HASH_2 0x00030000 /* Hash depth 2 */
|
||||
#define RCV_CONFIG_BUFLEN_MASK 0x0000FFF0 /* Buffer length bits 15:4. ie multiple of 16. */
|
||||
#define RCV_CONFIG_SKT_DIS 0x00000008 /* Disable socket detection on attn */
|
||||
/* Buffer length bits 15:4. ie multiple of 16. */
|
||||
#define RCV_CONFIG_BUFLEN_MASK 0x0000FFF0
|
||||
/* Disable socket detection on attn */
|
||||
#define RCV_CONFIG_SKT_DIS 0x00000008
|
||||
/*
|
||||
* Macro to determine RCV_CONFIG_BUFLEN based on maximum frame size.
|
||||
* We add 18 bytes for Sahara receive status and padding, plus 4 bytes for CRC,
|
||||
* and round up to nearest 16 byte boundary
|
||||
*/
|
||||
#define RCV_CONFIG_BUFSIZE(_MaxFrame) ((((_MaxFrame) + 22) + 15) & RCV_CONFIG_BUFLEN_MASK)
|
||||
#define RCV_CONFIG_BUFSIZE(_MaxFrame) \
|
||||
((((_MaxFrame) + 22) + 15) & RCV_CONFIG_BUFLEN_MASK)
|
||||
|
||||
#define XMT_CONFIG_RESET 0x80000000 /* XmtConfig register reset */
|
||||
/* XmtConfig register reset */
|
||||
#define XMT_CONFIG_RESET 0x80000000
|
||||
#define XMT_CONFIG_ENABLE 0x40000000 /* Enable transmit logic */
|
||||
#define XMT_CONFIG_MAC_PARITY 0x20000000 /* Inhibit MAC RAM parity error */
|
||||
#define XMT_CONFIG_BUF_PARITY 0x10000000 /* Inhibit D2F buffer parity error */
|
||||
#define XMT_CONFIG_MEM_PARITY 0x08000000 /* Inhibit 1T SRAM parity error */
|
||||
/* Inhibit MAC RAM parity error */
|
||||
#define XMT_CONFIG_MAC_PARITY 0x20000000
|
||||
/* Inhibit D2F buffer parity error */
|
||||
#define XMT_CONFIG_BUF_PARITY 0x10000000
|
||||
/* Inhibit 1T SRAM parity error */
|
||||
#define XMT_CONFIG_MEM_PARITY 0x08000000
|
||||
#define XMT_CONFIG_INVERT_PARITY 0x04000000 /* Invert MAC RAM parity */
|
||||
#define XMT_CONFIG_INITIAL_IPID 0x0000FFFF /* Initial IPID */
|
||||
|
||||
@ -254,45 +302,68 @@ struct sxg_hw_regs {
|
||||
#define AXGMAC_CFG0_MII_RESET 0x00010000 /* MII Management reset */
|
||||
|
||||
/* A-XGMAC Configuration Register 1 */
|
||||
#define AXGMAC_CFG1_XMT_PAUSE 0x80000000 /* Allow the sending of Pause frames */
|
||||
/* Allow the sending of Pause frames */
|
||||
#define AXGMAC_CFG1_XMT_PAUSE 0x80000000
|
||||
#define AXGMAC_CFG1_XMT_EN 0x40000000 /* Enable transmit */
|
||||
#define AXGMAC_CFG1_RCV_PAUSE 0x20000000 /* Allow the detection of Pause frames */
|
||||
/* Allow the detection of Pause frames */
|
||||
#define AXGMAC_CFG1_RCV_PAUSE 0x20000000
|
||||
#define AXGMAC_CFG1_RCV_EN 0x10000000 /* Enable receive */
|
||||
#define AXGMAC_CFG1_XMT_STATE 0x04000000 /* Current transmit state - READ ONLY */
|
||||
#define AXGMAC_CFG1_RCV_STATE 0x01000000 /* Current receive state - READ ONLY */
|
||||
#define AXGMAC_CFG1_XOFF_SHORT 0x00001000 /* Only pause for 64 slot on XOFF */
|
||||
#define AXGMAC_CFG1_XMG_FCS1 0x00000400 /* Delay transmit FCS 1 4-byte word */
|
||||
#define AXGMAC_CFG1_XMG_FCS2 0x00000800 /* Delay transmit FCS 2 4-byte words */
|
||||
#define AXGMAC_CFG1_XMG_FCS3 0x00000C00 /* Delay transmit FCS 3 4-byte words */
|
||||
#define AXGMAC_CFG1_RCV_FCS1 0x00000100 /* Delay receive FCS 1 4-byte word */
|
||||
#define AXGMAC_CFG1_RCV_FCS2 0x00000200 /* Delay receive FCS 2 4-byte words */
|
||||
#define AXGMAC_CFG1_RCV_FCS3 0x00000300 /* Delay receive FCS 3 4-byte words */
|
||||
#define AXGMAC_CFG1_PKT_OVERRIDE 0x00000080 /* Per-packet override enable */
|
||||
/* Current transmit state - READ ONLY */
|
||||
#define AXGMAC_CFG1_XMT_STATE 0x04000000
|
||||
/* Current receive state - READ ONLY */
|
||||
#define AXGMAC_CFG1_RCV_STATE 0x01000000
|
||||
/* Only pause for 64 slot on XOFF */
|
||||
#define AXGMAC_CFG1_XOFF_SHORT 0x00001000
|
||||
/* Delay transmit FCS 1 4-byte word */
|
||||
#define AXGMAC_CFG1_XMG_FCS1 0x00000400
|
||||
/* Delay transmit FCS 2 4-byte words */
|
||||
#define AXGMAC_CFG1_XMG_FCS2 0x00000800
|
||||
/* Delay transmit FCS 3 4-byte words */
|
||||
#define AXGMAC_CFG1_XMG_FCS3 0x00000C00
|
||||
/* Delay receive FCS 1 4-byte word */
|
||||
#define AXGMAC_CFG1_RCV_FCS1 0x00000100
|
||||
/* Delay receive FCS 2 4-byte words */
|
||||
#define AXGMAC_CFG1_RCV_FCS2 0x00000200
|
||||
/* Delay receive FCS 3 4-byte words */
|
||||
#define AXGMAC_CFG1_RCV_FCS3 0x00000300
|
||||
/* Per-packet override enable */
|
||||
#define AXGMAC_CFG1_PKT_OVERRIDE 0x00000080
|
||||
#define AXGMAC_CFG1_SWAP 0x00000040 /* Byte swap enable */
|
||||
#define AXGMAC_CFG1_SHORT_ASSERT 0x00000020 /* ASSERT srdrpfrm on short frame (<64) */
|
||||
#define AXGMAC_CFG1_RCV_STRICT 0x00000010 /* RCV only 802.3AE when CLEAR */
|
||||
/* ASSERT srdrpfrm on short frame (<64) */
|
||||
#define AXGMAC_CFG1_SHORT_ASSERT 0x00000020
|
||||
/* RCV only 802.3AE when CLEAR */
|
||||
#define AXGMAC_CFG1_RCV_STRICT 0x00000010
|
||||
#define AXGMAC_CFG1_CHECK_LEN 0x00000008 /* Verify frame length */
|
||||
#define AXGMAC_CFG1_GEN_FCS 0x00000004 /* Generate FCS */
|
||||
#define AXGMAC_CFG1_PAD_MASK 0x00000003 /* Mask for pad bits */
|
||||
#define AXGMAC_CFG1_PAD_64 0x00000001 /* Pad frames to 64 bytes */
|
||||
#define AXGMAC_CFG1_PAD_VLAN 0x00000002 /* Detect VLAN and pad to 68 bytes */
|
||||
/* Detect VLAN and pad to 68 bytes */
|
||||
#define AXGMAC_CFG1_PAD_VLAN 0x00000002
|
||||
#define AXGMAC_CFG1_PAD_68 0x00000003 /* Pad to 68 bytes */
|
||||
|
||||
/* A-XGMAC Configuration Register 2 */
|
||||
#define AXGMAC_CFG2_GEN_PAUSE 0x80000000 /* Generate single pause frame (test) */
|
||||
#define AXGMAC_CFG2_LF_MANUAL 0x08000000 /* Manual link fault sequence */
|
||||
#define AXGMAC_CFG2_LF_AUTO 0x04000000 /* Auto link fault sequence */
|
||||
#define AXGMAC_CFG2_LF_REMOTE 0x02000000 /* Remote link fault (READ ONLY) */
|
||||
#define AXGMAC_CFG2_LF_LOCAL 0x01000000 /* Local link fault (READ ONLY) */
|
||||
/* Generate single pause frame (test) */
|
||||
#define AXGMAC_CFG2_GEN_PAUSE 0x80000000
|
||||
/* Manual link fault sequence */
|
||||
#define AXGMAC_CFG2_LF_MANUAL 0x08000000
|
||||
/* Auto link fault sequence */
|
||||
#define AXGMAC_CFG2_LF_AUTO 0x04000000
|
||||
/* Remote link fault (READ ONLY) */
|
||||
#define AXGMAC_CFG2_LF_REMOTE 0x02000000
|
||||
/* Local link fault (READ ONLY) */
|
||||
#define AXGMAC_CFG2_LF_LOCAL 0x01000000
|
||||
#define AXGMAC_CFG2_IPG_MASK 0x001F0000 /* Inter packet gap */
|
||||
#define AXGMAC_CFG2_IPG_SHIFT 16
|
||||
#define AXGMAC_CFG2_PAUSE_XMT 0x00008000 /* Pause transmit module */
|
||||
#define AXGMAC_CFG2_IPG_EXTEN 0x00000020 /* Enable IPG extension algorithm */
|
||||
/* Enable IPG extension algorithm */
|
||||
#define AXGMAC_CFG2_IPG_EXTEN 0x00000020
|
||||
#define AXGMAC_CFG2_IPGEX_MASK 0x0000001F /* IPG extension */
|
||||
|
||||
/* A-XGMAC Configuration Register 3 */
|
||||
#define AXGMAC_CFG3_RCV_DROP 0xFFFF0000 /* Receive frame drop filter */
|
||||
#define AXGMAC_CFG3_RCV_DONT_CARE 0x0000FFFF /* Receive frame don't care filter */
|
||||
/* Receive frame drop filter */
|
||||
#define AXGMAC_CFG3_RCV_DROP 0xFFFF0000
|
||||
/* Receive frame don't care filter */
|
||||
#define AXGMAC_CFG3_RCV_DONT_CARE 0x0000FFFF
|
||||
|
||||
/* A-XGMAC Station Address Register - Octets 1-4 */
|
||||
#define AXGMAC_SARLOW_OCTET_ONE 0xFF000000 /* First octet */
|
||||
@ -305,9 +376,11 @@ struct sxg_hw_regs {
|
||||
#define AXGMAC_SARHIGH_OCTET_SIX 0x00FF0000 /* Sixth octet */
|
||||
|
||||
/* A-XGMAC Maximum frame length register */
|
||||
#define AXGMAC_MAXFRAME_XMT 0x3FFF0000 /* Maximum transmit frame length */
|
||||
/* Maximum transmit frame length */
|
||||
#define AXGMAC_MAXFRAME_XMT 0x3FFF0000
|
||||
#define AXGMAC_MAXFRAME_XMT_SHIFT 16
|
||||
#define AXGMAC_MAXFRAME_RCV 0x0000FFFF /* Maximum receive frame length */
|
||||
/* Maximum receive frame length */
|
||||
#define AXGMAC_MAXFRAME_RCV 0x0000FFFF
|
||||
/*
|
||||
* This register doesn't need to be written for standard MTU.
|
||||
* For jumbo, I'll just statically define the value here. This
|
||||
@ -323,25 +396,32 @@ struct sxg_hw_regs {
|
||||
/* A-XGMAC AMIIM Command Register */
|
||||
#define AXGMAC_AMIIM_CMD_START 0x00000008 /* Command start */
|
||||
#define AXGMAC_AMIIM_CMD_MASK 0x00000007 /* Command */
|
||||
#define AXGMAC_AMIIM_CMD_LEGACY_WRITE 1 /* 10/100/1000 Mbps Phy Write */
|
||||
#define AXGMAC_AMIIM_CMD_LEGACY_READ 2 /* 10/100/1000 Mbps Phy Read */
|
||||
/* 10/100/1000 Mbps Phy Write */
|
||||
#define AXGMAC_AMIIM_CMD_LEGACY_WRITE 1
|
||||
/* 10/100/1000 Mbps Phy Read */
|
||||
#define AXGMAC_AMIIM_CMD_LEGACY_READ 2
|
||||
#define AXGMAC_AMIIM_CMD_MONITOR_SINGLE 3 /* Monitor single PHY */
|
||||
#define AXGMAC_AMIIM_CMD_MONITOR_MULTIPLE 4 /* Monitor multiple contiguous PHYs */
|
||||
#define AXGMAC_AMIIM_CMD_10G_OPERATION 5 /* Present AMIIM Field Reg */
|
||||
#define AXGMAC_AMIIM_CMD_CLEAR_LINK_FAIL 6 /* Clear Link Fail Bit in MIIM */
|
||||
/* Monitor multiple contiguous PHYs */
|
||||
#define AXGMAC_AMIIM_CMD_MONITOR_MULTIPLE 4
|
||||
/* Present AMIIM Field Reg */
|
||||
#define AXGMAC_AMIIM_CMD_10G_OPERATION 5
|
||||
/* Clear Link Fail Bit in MIIM */
|
||||
#define AXGMAC_AMIIM_CMD_CLEAR_LINK_FAIL 6
|
||||
|
||||
/* A-XGMAC AMIIM Field Register */
|
||||
#define AXGMAC_AMIIM_FIELD_ST 0xC0000000 /* 2-bit ST field */
|
||||
#define AXGMAC_AMIIM_FIELD_ST_SHIFT 30
|
||||
#define AXGMAC_AMIIM_FIELD_OP 0x30000000 /* 2-bit OP field */
|
||||
#define AXGMAC_AMIIM_FIELD_OP_SHIFT 28
|
||||
#define AXGMAC_AMIIM_FIELD_PORT_ADDR 0x0F800000 /* Port address field (hstphyadx in spec) */
|
||||
/* Port address field (hstphyadx in spec) */
|
||||
#define AXGMAC_AMIIM_FIELD_PORT_ADDR 0x0F800000
|
||||
#define AXGMAC_AMIIM_FIELD_PORT_SHIFT 23
|
||||
#define AXGMAC_AMIIM_FIELD_DEV_ADDR 0x007C0000 /* Device address field (hstregadx in spec) */
|
||||
/* Device address field (hstregadx in spec) */
|
||||
#define AXGMAC_AMIIM_FIELD_DEV_ADDR 0x007C0000
|
||||
#define AXGMAC_AMIIM_FIELD_DEV_SHIFT 18
|
||||
#define AXGMAC_AMIIM_FIELD_TA 0x00030000 /* 2-bit TA field */
|
||||
#define AXGMAC_AMIIM_FIELD_TA_SHIFT 16
|
||||
#define AXGMAC_AMIIM_FIELD_DATA 0x0000FFFF // Data field
|
||||
#define AXGMAC_AMIIM_FIELD_DATA 0x0000FFFF /* Data field */
|
||||
|
||||
/* Values for the AXGMAC_AMIIM_FIELD_OP field in the A-XGMAC AMIIM Field Register */
|
||||
#define MIIM_OP_ADDR 0 /* MIIM Address set operation */
|
||||
@ -349,45 +429,72 @@ struct sxg_hw_regs {
|
||||
#define MIIM_OP_READ 2 /* MIIM Read register operation */
|
||||
#define MIIM_OP_ADDR_SHIFT (MIIM_OP_ADDR << AXGMAC_AMIIM_FIELD_OP_SHIFT)
|
||||
|
||||
/* Values for the AXGMAC_AMIIM_FIELD_PORT_ADDR field in the A-XGMAC AMIIM Field Register */
|
||||
/*
|
||||
* Values for the AXGMAC_AMIIM_FIELD_PORT_ADDR field in the A-XGMAC AMIIM
|
||||
* Field Register
|
||||
*/
|
||||
#define MIIM_PORT_NUM 1 /* All Sahara MIIM modules use port 1 */
|
||||
|
||||
/* Values for the AXGMAC_AMIIM_FIELD_DEV_ADDR field in the A-XGMAC AMIIM Field Register */
|
||||
#define MIIM_DEV_PHY_PMA 1 /* PHY PMA/PMD module MIIM device number */
|
||||
#define MIIM_DEV_PHY_PCS 3 /* PHY PCS module MIIM device number */
|
||||
#define MIIM_DEV_PHY_XS 4 /* PHY XS module MIIM device number */
|
||||
/*
|
||||
* Values for the AXGMAC_AMIIM_FIELD_DEV_ADDR field in the A-XGMAC AMIIM
|
||||
* Field Register
|
||||
*/
|
||||
/* PHY PMA/PMD module MIIM device number */
|
||||
#define MIIM_DEV_PHY_PMA 1
|
||||
/* PHY PCS module MIIM device number */
|
||||
#define MIIM_DEV_PHY_PCS 3
|
||||
/* PHY XS module MIIM device number */
|
||||
#define MIIM_DEV_PHY_XS 4
|
||||
#define MIIM_DEV_XGXS 5 /* XGXS MIIM device number */
|
||||
|
||||
/* Values for the AXGMAC_AMIIM_FIELD_TA field in the A-XGMAC AMIIM Field Register */
|
||||
/*
|
||||
* Values for the AXGMAC_AMIIM_FIELD_TA field in the A-XGMAC AMIIM Field
|
||||
* Register
|
||||
*/
|
||||
#define MIIM_TA_10GB 2 /* set to 2 for 10 GB operation */
|
||||
|
||||
/* A-XGMAC AMIIM Configuration Register */
|
||||
#define AXGMAC_AMIIM_CFG_NOPREAM 0x00000080 /* Bypass preamble of mngmt frame */
|
||||
#define AXGMAC_AMIIM_CFG_HALF_CLOCK 0x0000007F /* half-clock duration of MDC output */
|
||||
/* Bypass preamble of mngmt frame */
|
||||
#define AXGMAC_AMIIM_CFG_NOPREAM 0x00000080
|
||||
/* half-clock duration of MDC output */
|
||||
#define AXGMAC_AMIIM_CFG_HALF_CLOCK 0x0000007F
|
||||
|
||||
/* A-XGMAC AMIIM Indicator Register */
|
||||
#define AXGMAC_AMIIM_INDC_LINK 0x00000010 /* Link status from legacy PHY or MMD */
|
||||
#define AXGMAC_AMIIM_INDC_MPHY 0x00000008 /* Multiple phy operation in progress */
|
||||
#define AXGMAC_AMIIM_INDC_SPHY 0x00000004 /* Single phy operation in progress */
|
||||
#define AXGMAC_AMIIM_INDC_MON 0x00000002 /* Single or multiple monitor cmd */
|
||||
#define AXGMAC_AMIIM_INDC_BUSY 0x00000001 /* Set until cmd operation complete */
|
||||
/* Link status from legacy PHY or MMD */
|
||||
#define AXGMAC_AMIIM_INDC_LINK 0x00000010
|
||||
/* Multiple phy operation in progress */
|
||||
#define AXGMAC_AMIIM_INDC_MPHY 0x00000008
|
||||
/* Single phy operation in progress */
|
||||
#define AXGMAC_AMIIM_INDC_SPHY 0x00000004
|
||||
/* Single or multiple monitor cmd */
|
||||
#define AXGMAC_AMIIM_INDC_MON 0x00000002
|
||||
/* Set until cmd operation complete */
|
||||
#define AXGMAC_AMIIM_INDC_BUSY 0x00000001
|
||||
|
||||
/* Link Status and Control Register */
|
||||
#define LS_PHY_CLR_RESET 0x80000000 /* Clear reset signal to PHY */
|
||||
#define LS_SERDES_POWER_DOWN 0x40000000 /* Power down the Sahara Serdes */
|
||||
#define LS_XGXS_ENABLE 0x20000000 /* Enable the XAUI XGXS logic */
|
||||
#define LS_XGXS_CTL 0x10000000 /* Hold XAUI XGXS logic reset until Serdes is up */
|
||||
#define LS_SERDES_DOWN 0x08000000 /* When 0, XAUI Serdes is up and initialization is complete */
|
||||
#define LS_TRACE_DOWN 0x04000000 /* When 0, Trace Serdes is up and initialization is complete */
|
||||
#define LS_PHY_CLK_25MHZ 0x02000000 /* Set PHY clock to 25 MHz (else 156.125 MHz) */
|
||||
/* Hold XAUI XGXS logic reset until Serdes is up */
|
||||
#define LS_XGXS_CTL 0x10000000
|
||||
/* When 0, XAUI Serdes is up and initialization is complete */
|
||||
#define LS_SERDES_DOWN 0x08000000
|
||||
/* When 0, Trace Serdes is up and initialization is complete */
|
||||
#define LS_TRACE_DOWN 0x04000000
|
||||
/* Set PHY clock to 25 MHz (else 156.125 MHz) */
|
||||
#define LS_PHY_CLK_25MHZ 0x02000000
|
||||
#define LS_PHY_CLK_EN 0x01000000 /* Enable clock to PHY */
|
||||
#define LS_XAUI_LINK_UP 0x00000010 /* XAUI link is up */
|
||||
#define LS_XAUI_LINK_CHNG 0x00000008 /* XAUI link status has changed */
|
||||
/* XAUI link status has changed */
|
||||
#define LS_XAUI_LINK_CHNG 0x00000008
|
||||
#define LS_LINK_ALARM 0x00000004 /* Link alarm pin */
|
||||
#define LS_ATTN_CTRL_MASK 0x00000003 /* Mask link attention control bits */
|
||||
/* Mask link attention control bits */
|
||||
#define LS_ATTN_CTRL_MASK 0x00000003
|
||||
#define LS_ATTN_ALARM 0x00000000 /* 00 => Attn on link alarm */
|
||||
#define LS_ATTN_ALARM_OR_STAT_CHNG 0x00000001 /* 01 => Attn on link alarm or status change */
|
||||
#define LS_ATTN_STAT_CHNG 0x00000002 /* 10 => Attn on link status change */
|
||||
/* 01 => Attn on link alarm or status change */
|
||||
#define LS_ATTN_ALARM_OR_STAT_CHNG 0x00000001
|
||||
/* 10 => Attn on link status change */
|
||||
#define LS_ATTN_STAT_CHNG 0x00000002
|
||||
#define LS_ATTN_NONE 0x00000003 /* 11 => no Attn */
|
||||
|
||||
/* Link Address High Registers */
|
||||
@ -423,7 +530,8 @@ struct sxg_hw_regs {
|
||||
#define XGXS_CONTROL1_SPEED1 0x2000 /* 0 = unspecified, 1 = 10Gb+ */
|
||||
#define XGXS_CONTROL1_LOWPOWER 0x0400 /* 1 = Low power mode */
|
||||
#define XGXS_CONTROL1_SPEED2 0x0040 /* Same as SPEED1 (?) */
|
||||
#define XGXS_CONTROL1_SPEED 0x003C /* Everything reserved except zero (?) */
|
||||
/* Everything reserved except zero (?) */
|
||||
#define XGXS_CONTROL1_SPEED 0x003C
|
||||
|
||||
/* XS Status 1 register bit definitions */
|
||||
#define XGXS_STATUS1_FAULT 0x0080 /* Fault detected */
|
||||
@ -439,7 +547,7 @@ struct sxg_hw_regs {
|
||||
#define XGXS_DEVICES_PCS 0x0008 /* PCS Present */
|
||||
#define XGXS_DEVICES_WIS 0x0004 /* WIS Present */
|
||||
#define XGXS_DEVICES_PMD 0x0002 /* PMD/PMA Present */
|
||||
#define XGXS_DEVICES_CLAUSE22 0x0001 /* Clause 22 registers present */
|
||||
#define XGXS_DEVICES_CLAUSE22 0x0001 /* Clause 22 registers present*/
|
||||
|
||||
/* XS Devices High register bit definitions */
|
||||
#define XGXS_DEVICES_VENDOR2 0x8000 /* Vendor specific device 2 */
|
||||
@ -478,7 +586,10 @@ struct sxg_hw_regs {
|
||||
*
|
||||
* Full register descriptions can be found in PHY/XENPAK/IEEE specs
|
||||
*/
|
||||
/* LASI (Link Alarm Status Interrupt) Registers (located in MIIM_DEV_PHY_PMA device) */
|
||||
/*
|
||||
* LASI (Link Alarm Status Interrupt) Registers (located in
|
||||
* MIIM_DEV_PHY_PMA device)
|
||||
*/
|
||||
#define LASI_RX_ALARM_CONTROL 0x9000 /* LASI RX_ALARM Control */
|
||||
#define LASI_TX_ALARM_CONTROL 0x9001 /* LASI TX_ALARM Control */
|
||||
#define LASI_CONTROL 0x9002 /* LASI Control */
|
||||
@ -487,9 +598,12 @@ struct sxg_hw_regs {
|
||||
#define LASI_STATUS 0x9005 /* LASI Status */
|
||||
|
||||
/* LASI_CONTROL bit definitions */
|
||||
#define LASI_CTL_RX_ALARM_ENABLE 0x0004 /* Enable RX_ALARM interrupts */
|
||||
#define LASI_CTL_TX_ALARM_ENABLE 0x0002 /* Enable TX_ALARM interrupts */
|
||||
#define LASI_CTL_LS_ALARM_ENABLE 0x0001 /* Enable Link Status interrupts */
|
||||
/* Enable RX_ALARM interrupts */
|
||||
#define LASI_CTL_RX_ALARM_ENABLE 0x0004
|
||||
/* Enable TX_ALARM interrupts */
|
||||
#define LASI_CTL_TX_ALARM_ENABLE 0x0002
|
||||
/* Enable Link Status interrupts */
|
||||
#define LASI_CTL_LS_ALARM_ENABLE 0x0001
|
||||
|
||||
/* LASI_STATUS bit definitions */
|
||||
#define LASI_STATUS_RX_ALARM 0x0004 /* RX_ALARM status */
|
||||
@ -559,13 +673,20 @@ struct phy_ucode {
|
||||
#pragma pack(push, 1)
|
||||
struct xmt_desc {
|
||||
ushort XmtLen; /* word 0, bits [15:0] - transmit length */
|
||||
unsigned char XmtCtl; /* word 0, bits [23:16] - transmit control byte */
|
||||
unsigned char Cmd; /* word 0, bits [31:24] - transmit command plus misc. */
|
||||
u32 XmtBufId; /* word 1, bits [31:0] - transmit buffer ID */
|
||||
unsigned char TcpStrt; /* word 2, bits [7:0] - byte address of TCP header */
|
||||
unsigned char IpStrt; /* word 2, bits [15:8] - byte address of IP header */
|
||||
ushort IpCkSum; /* word 2, bits [31:16] - partial IP checksum */
|
||||
ushort TcpCkSum; /* word 3, bits [15:0] - partial TCP checksum */
|
||||
/* word 0, bits [23:16] - transmit control byte */
|
||||
unsigned char XmtCtl;
|
||||
/* word 0, bits [31:24] - transmit command plus misc. */
|
||||
unsigned char Cmd;
|
||||
/* word 1, bits [31:0] - transmit buffer ID */
|
||||
u32 XmtBufId;
|
||||
/* word 2, bits [7:0] - byte address of TCP header */
|
||||
unsigned char TcpStrt;
|
||||
/* word 2, bits [15:8] - byte address of IP header */
|
||||
unsigned char IpStrt;
|
||||
/* word 2, bits [31:16] - partial IP checksum */
|
||||
ushort IpCkSum;
|
||||
/* word 3, bits [15:0] - partial TCP checksum */
|
||||
ushort TcpCkSum;
|
||||
ushort Rsvd1; /* word 3, bits [31:16] - PAD */
|
||||
u32 Rsvd2; /* word 4, bits [31:0] - PAD */
|
||||
u32 Rsvd3; /* word 5, bits [31:0] - PAD */
|
||||
@ -580,7 +701,8 @@ struct xmt_desc {
|
||||
#define XMT_DESC_CMD_CSUM_INSERT 1 /* checksum insert descriptor */
|
||||
#define XMT_DESC_CMD_FORMAT 2 /* format descriptor */
|
||||
#define XMT_DESC_CMD_PRIME 3 /* prime descriptor */
|
||||
#define XMT_DESC_CMD_CODE_SHFT 6 /* comand code shift (shift to bits [31:30] in word 0) */
|
||||
/* comand code shift (shift to bits [31:30] in word 0) */
|
||||
#define XMT_DESC_CMD_CODE_SHFT 6
|
||||
/* shifted command codes */
|
||||
#define XMT_RAW_SEND (XMT_DESC_CMD_RAW_SEND << XMT_DESC_CMD_CODE_SHFT)
|
||||
#define XMT_CSUM_INSERT (XMT_DESC_CMD_CSUM_INSERT << XMT_DESC_CMD_CODE_SHFT)
|
||||
@ -591,31 +713,46 @@ struct xmt_desc {
|
||||
* struct xmt_desc Control Byte (XmtCtl) definitions
|
||||
* NOTE: These bits do not work on Sahara (Rev A)!
|
||||
*/
|
||||
#define XMT_CTL_PAUSE_FRAME 0x80 /* current frame is a pause control frame (for statistics) */
|
||||
#define XMT_CTL_CONTROL_FRAME 0x40 /* current frame is a control frame (for statistics) */
|
||||
/* current frame is a pause control frame (for statistics) */
|
||||
#define XMT_CTL_PAUSE_FRAME 0x80
|
||||
/* current frame is a control frame (for statistics) */
|
||||
#define XMT_CTL_CONTROL_FRAME 0x40
|
||||
#define XMT_CTL_PER_PKT_QUAL 0x20 /* per packet qualifier */
|
||||
#define XMT_CTL_PAD_MODE_NONE 0x00 /* do not pad frame */
|
||||
#define XMT_CTL_PAD_MODE_64 0x08 /* pad frame to 64 bytes */
|
||||
#define XMT_CTL_PAD_MODE_VLAN_68 0x10 /* pad frame to 64 bytes, and VLAN frames to 68 bytes */
|
||||
/* pad frame to 64 bytes, and VLAN frames to 68 bytes */
|
||||
#define XMT_CTL_PAD_MODE_VLAN_68 0x10
|
||||
#define XMT_CTL_PAD_MODE_68 0x18 /* pad frame to 68 bytes */
|
||||
#define XMT_CTL_GEN_FCS 0x04 /* generate FCS (CRC) for this frame */
|
||||
/* generate FCS (CRC) for this frame */
|
||||
#define XMT_CTL_GEN_FCS 0x04
|
||||
#define XMT_CTL_DELAY_FCS_0 0x00 /* do not delay FCS calcution */
|
||||
#define XMT_CTL_DELAY_FCS_1 0x01 /* delay FCS calculation by 1 (4-byte) word */
|
||||
#define XMT_CTL_DELAY_FCS_2 0x02 /* delay FCS calculation by 2 (4-byte) words */
|
||||
#define XMT_CTL_DELAY_FCS_3 0x03 /* delay FCS calculation by 3 (4-byte) words */
|
||||
/* delay FCS calculation by 1 (4-byte) word */
|
||||
#define XMT_CTL_DELAY_FCS_1 0x01
|
||||
/* delay FCS calculation by 2 (4-byte) words */
|
||||
#define XMT_CTL_DELAY_FCS_2 0x02
|
||||
/* delay FCS calculation by 3 (4-byte) words */
|
||||
#define XMT_CTL_DELAY_FCS_3 0x03
|
||||
|
||||
/* struct xmt_desc XmtBufId definition */
|
||||
#define XMT_BUF_ID_SHFT 8 /* The Xmt buffer ID is formed by dividing */
|
||||
/* the buffer (DRAM) address by 256 (or << 8) */
|
||||
/*
|
||||
* The Xmt buffer ID is formed by dividing the buffer (DRAM) address
|
||||
* by 256 (or << 8)
|
||||
*/
|
||||
|
||||
#define XMT_BUF_ID_SHFT 8
|
||||
|
||||
/* Receiver Sequencer Definitions */
|
||||
|
||||
/* Receive Event Queue (queues 3 - 6) bit definitions */
|
||||
#define RCV_EVTQ_RBFID_MASK 0x0000FFFF /* bit mask for the Receive Buffer ID */
|
||||
/* bit mask for the Receive Buffer ID */
|
||||
#define RCV_EVTQ_RBFID_MASK 0x0000FFFF
|
||||
|
||||
/* Receive Buffer ID definition */
|
||||
#define RCV_BUF_ID_SHFT 5 /* The Rcv buffer ID is formed by dividing */
|
||||
/* the buffer (DRAM) address by 32 (or << 5) */
|
||||
/*
|
||||
* The Rcv buffer ID is formed by dividing the buffer (DRAM) address
|
||||
* by 32 (or << 5)
|
||||
*/
|
||||
#define RCV_BUF_ID_SHFT 5
|
||||
|
||||
/*
|
||||
* Format of the 18 byte Receive Buffer returned by the
|
||||
@ -628,8 +765,10 @@ struct rcv_buf_hdr {
|
||||
union {
|
||||
ushort TcpCsum; /* TCP checksum */
|
||||
struct {
|
||||
unsigned char TcpCsumL; /* lower 8 bits of the TCP checksum */
|
||||
unsigned char LinkHash; /* Link hash (multicast frames only) */
|
||||
/* lower 8 bits of the TCP checksum */
|
||||
unsigned char TcpCsumL;
|
||||
/* Link hash (multicast frames only) */
|
||||
unsigned char LinkHash;
|
||||
};
|
||||
};
|
||||
ushort SktHash; /* Socket hash */
|
||||
@ -657,7 +796,7 @@ struct rcv_buf_hdr {
|
||||
#define LOCAL_C_Q 10 /* Spare local Queue */
|
||||
#define FSM_EVT_Q 11 /* Finite-State-Machine Event Queue */
|
||||
#define SBF_PAL_Q 12 /* System Buffer Physical Address (low) Queue */
|
||||
#define SBF_PAH_Q 13 /* System Buffer Physical Address (high) Queue */
|
||||
#define SBF_PAH_Q 13 /* System Buffer Physical Address (high) Queue*/
|
||||
#define SBF_VAL_Q 14 /* System Buffer Virtual Address (low) Queue */
|
||||
#define SBF_VAH_Q 15 /* System Buffer Virtual Address (high) Queue */
|
||||
/* Egress (write only) queue numbers */
|
||||
@ -674,27 +813,38 @@ struct rcv_buf_hdr {
|
||||
#define RCV_BUF_Q 26 /* Receive Buffer Queue */
|
||||
|
||||
/* Bit definitions for the Proxy Command queues (PXL_CMD_Q and PXH_CMD_Q) */
|
||||
#define PXY_COPY_EN 0x00200000 /* enable copy of xmt descriptor to xmt command queue */
|
||||
/* enable copy of xmt descriptor to xmt command queue */
|
||||
#define PXY_COPY_EN 0x00200000
|
||||
#define PXY_SIZE_16 0x00000000 /* copy 16 bytes */
|
||||
#define PXY_SIZE_32 0x00100000 /* copy 32 bytes */
|
||||
|
||||
/* SXG EEPROM/Flash Configuration Definitions */
|
||||
|
||||
/* Location of configuration data in EEPROM or Flash */
|
||||
#define EEPROM_CONFIG_START_ADDR 0x00 /* start addr for config info in EEPROM */
|
||||
#define FLASH_CONFIG_START_ADDR 0x80 /* start addr for config info in Flash */
|
||||
/* start addr for config info in EEPROM */
|
||||
#define EEPROM_CONFIG_START_ADDR 0x00
|
||||
/* start addr for config info in Flash */
|
||||
#define FLASH_CONFIG_START_ADDR 0x80
|
||||
|
||||
/* Configuration data section defines */
|
||||
#define HW_CFG_SECTION_SIZE 512 /* size of H/W section */
|
||||
#define HW_CFG_SECTION_SIZE_A 256 /* size of H/W section (Sahara rev A) */
|
||||
#define SW_CFG_SECTION_START 512 /* starting location (offset) of S/W section */
|
||||
#define SW_CFG_SECTION_START_A 256 /* starting location (offset) of S/W section (Sahara rev A) */
|
||||
/* starting location (offset) of S/W section */
|
||||
#define SW_CFG_SECTION_START 512
|
||||
/* starting location (offset) of S/W section (Sahara rev A) */
|
||||
#define SW_CFG_SECTION_START_A 256
|
||||
#define SW_CFG_SECTION_SIZE 128 /* size of S/W section */
|
||||
/*
|
||||
* H/W configuration data magic word Goes in Addr field of first
|
||||
* struct hw_cfg_data entry
|
||||
*/
|
||||
#define HW_CFG_MAGIC_WORD 0xA5A5
|
||||
/*
|
||||
* H/W configuration data terminator Goes in Addr field of last
|
||||
* struct hw_cfg_data entry
|
||||
*/
|
||||
#define HW_CFG_TERMINATOR 0xFFFF
|
||||
|
||||
#define HW_CFG_MAGIC_WORD 0xA5A5 /* H/W configuration data magic word */
|
||||
/* Goes in Addr field of first struct hw_cfg_data entry */
|
||||
#define HW_CFG_TERMINATOR 0xFFFF /* H/W configuration data terminator */
|
||||
/* Goes in Addr field of last struct hw_cfg_data entry */
|
||||
#define SW_CFG_MAGIC_WORD 0x5A5A /* S/W configuration data magic word */
|
||||
|
||||
#pragma pack(push, 1)
|
||||
@ -709,11 +859,13 @@ struct hw_cfg_data {
|
||||
|
||||
/*
|
||||
* Number of struct hw_cfg_data structures to put in the configuration data
|
||||
* data structure (struct sxg_config or struct sxg_config_a). The number is computed
|
||||
* to fill the entire H/W config section of the structure.
|
||||
* data structure (struct sxg_config or struct sxg_config_a). The number is
|
||||
* computed to fill the entire H/W config section of the structure.
|
||||
*/
|
||||
#define NUM_HW_CFG_ENTRIES (HW_CFG_SECTION_SIZE / sizeof(struct hw_cfg_data))
|
||||
#define NUM_HW_CFG_ENTRIES_A (HW_CFG_SECTION_SIZE_A / sizeof(struct hw_cfg_data))
|
||||
#define NUM_HW_CFG_ENTRIES \
|
||||
(HW_CFG_SECTION_SIZE / sizeof(struct hw_cfg_data))
|
||||
#define NUM_HW_CFG_ENTRIES_A \
|
||||
(HW_CFG_SECTION_SIZE_A / sizeof(struct hw_cfg_data))
|
||||
|
||||
/* MAC address structure */
|
||||
struct sxg_config_mac {
|
||||
@ -800,10 +952,13 @@ struct sxg_config_a {
|
||||
* at compile time.
|
||||
*/
|
||||
compile_time_assert (offsetof(struct sxg_config, SwCfg) == SW_CFG_SECTION_START);
|
||||
compile_time_assert (sizeof(struct sxg_config) == HW_CFG_SECTION_SIZE + SW_CFG_SECTION_SIZE);
|
||||
compile_time_assert (sizeof(struct sxg_config) == HW_CFG_SECTION_SIZE
|
||||
+ SW_CFG_SECTION_SIZE);
|
||||
|
||||
compile_time_assert (offsetof(struct sxg_config_a, SwCfg) == SW_CFG_SECTION_START_A);
|
||||
compile_time_assert (sizeof(struct sxg_config_a) == HW_CFG_SECTION_SIZE_A + SW_CFG_SECTION_SIZE);
|
||||
compile_time_assert (offsetof(struct sxg_config_a, SwCfg)
|
||||
== SW_CFG_SECTION_START_A);
|
||||
compile_time_assert (sizeof(struct sxg_config_a) == HW_CFG_SECTION_SIZE_A
|
||||
+ SW_CFG_SECTION_SIZE);
|
||||
#endif
|
||||
/*
|
||||
* Structure used to pass information between driver and user-mode
|
||||
@ -811,7 +966,8 @@ compile_time_assert (sizeof(struct sxg_config_a) == HW_CFG_SECTION_SIZE_A + SW_C
|
||||
*/
|
||||
struct adapt_userinfo {
|
||||
bool LinkUp;
|
||||
/* u32 LinkState; * use LinkUp - any need for other states? */
|
||||
/* use LinkUp - any need for other states? */
|
||||
/* u32 LinkState; */
|
||||
u32 LinkSpeed; /* not currently needed */
|
||||
u32 LinkDuplex; /* not currently needed */
|
||||
u32 Port; /* not currently needed */
|
||||
@ -837,11 +993,16 @@ enum ASIC_TYPE{
|
||||
/* Sahara (ASIC level) defines */
|
||||
#define SAHARA_GRAM_SIZE 0x020000 /* GRAM size - 128 KB */
|
||||
#define SAHARA_DRAM_SIZE 0x200000 /* DRAM size - 2 MB */
|
||||
#define SAHARA_QRAM_SIZE 0x004000 /* QRAM size - 16K entries (64 KB) */
|
||||
#define SAHARA_WCS_SIZE 0x002000 /* WCS - 8K instructions (x 108 bits) */
|
||||
/* QRAM size - 16K entries (64 KB) */
|
||||
#define SAHARA_QRAM_SIZE 0x004000
|
||||
/* WCS - 8K instructions (x 108 bits) */
|
||||
#define SAHARA_WCS_SIZE 0x002000
|
||||
|
||||
/* Arabia (board level) defines */
|
||||
#define FLASH_SIZE 0x080000 /* 512 KB (4 Mb) */
|
||||
#define EEPROM_SIZE_XFMR 1024 /* EEPROM size (bytes), including xfmr area */
|
||||
#define EEPROM_SIZE_NO_XFMR 640 /* EEPROM size excluding xfmr area (512 + 128) */
|
||||
#define EEPROM_SIZE_REV_A 512 /* EEPROM size for Sahara rev A */
|
||||
/* EEPROM size (bytes), including xfmr area */
|
||||
#define EEPROM_SIZE_XFMR 1024
|
||||
/* EEPROM size excluding xfmr area (512 + 128) */
|
||||
#define EEPROM_SIZE_NO_XFMR 640
|
||||
/* EEPROM size for Sahara rev A */
|
||||
#define EEPROM_SIZE_REV_A 512
|
||||
|
||||
@ -14,7 +14,10 @@
|
||||
* type of transceiver.
|
||||
*/
|
||||
|
||||
/* Download for AEL2005C PHY with SR/LR transceiver (10GBASE-SR or 10GBASE-LR) */
|
||||
/*
|
||||
* Download for AEL2005C PHY with SR/LR transceiver
|
||||
* (10GBASE-SR or 10GBASE-LR)
|
||||
*/
|
||||
static struct phy_ucode PhyUcode[] = {
|
||||
/*
|
||||
* NOTE: An address of 0 is a special case. When the download routine
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user