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pinctrl: msm: Remove explicit barriers from mmio ops where unneeded

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For the vast majority of mmio operations in this driver, explicit memory
barriers aren't needed either because a data dependency between a read
and write already exists, or because of the presence of the spin locks
which execute a full memory barrier.

Removing all the unneeded explicit barriers considerably reduces
overhead for pinctrl operations, which in turn benefits things like i2c.

Change-Id: I566e9189fa0d392f242395b43aefbb9f324c1900
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
Signed-off-by: Richard Raya <rdxzv.dev@gmail.com>
This commit is contained in:
Sultan Alsawaf 2020-05-30 00:44:06 -07:00 committed by Richard Raya
parent a9566ccc56
commit d774137330
1 changed files with 5 additions and 5 deletions
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10
drivers/pinctrl/qcom/pinctrl-msm.c
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@ -518,7 +518,7 @@ static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, in
val = readl_relaxed(base + g->ctl_reg);
val |= BIT(g->oe_bit);
writel(val, base + g->ctl_reg);
writel_relaxed(val, base + g->ctl_reg);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
@ -674,11 +674,11 @@ static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
base = reassign_pctrl_reg(pctrl->soc, d->hwirq);
do {
val = readl(base + g->io_reg) & BIT(g->in_bit);
val = readl_relaxed(base + g->io_reg) & BIT(g->in_bit);
pol = readl_relaxed(base + g->intr_cfg_reg);
pol ^= BIT(g->intr_polarity_bit);
writel(pol, base + g->intr_cfg_reg);
writel_relaxed(pol, base + g->intr_cfg_reg);
val2 = readl_relaxed(base + g->io_reg) & BIT(g->in_bit);
intstat = readl_relaxed(base + g->intr_status_reg);
@ -738,7 +738,7 @@ static void msm_gpio_irq_enable(struct irq_data *d)
val = readl_relaxed(base + g->intr_cfg_reg);
val |= BIT(g->intr_enable_bit);
writel(val, base + g->intr_cfg_reg);
writel_relaxed(val, base + g->intr_cfg_reg);
set_bit(d->hwirq, pctrl->enabled_irqs);
@ -889,7 +889,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
} else {
BUG();
}
writel(val, base + g->intr_cfg_reg);
writel_relaxed(val, base + g->intr_cfg_reg);
if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
msm_gpio_update_dual_edge_pos(pctrl, g, d);