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ARM: dts: msm: Add MPM interrupt controller for qcs405

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Add mpm interrupt controller as SOC interrupt parent and
as a child domain under intc for qcs405.

Change-Id: I3fc3a24d7a99c64fe1ab615b37239aec0b8e13c1
Signed-off-by: Raghavendra Kakarla <rkakarla@codeaurora.org>
This commit is contained in:
Raghavendra Kakarla 2018-05-14 15:35:06 +05:30 committed by Gerrit - the friendly Code Review server
parent 672f6fe4b1
commit e1ba9df10c
2 changed files with 23 additions and 2 deletions
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3
arch/arm64/boot/dts/qcom/qcs405-pinctrl.dtsi
View File

@ -15,10 +15,11 @@
tlmm: pinctrl@1000000 {
compatible = "qcom,qcs405-pinctrl";
reg = <0x1000000 0x300000>;
interrupts = <0 208 0>;
interrupts-extended = <&wakegic GIC_SPI 208 IRQ_TYPE_NONE>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&wakegpio>;
#interrupt-cells = <2>;
pmx-uartconsole {

22
arch/arm64/boot/dts/qcom/qcs405.dtsi
View File

@ -23,7 +23,7 @@
model = "Qualcomm Technologies, Inc. QCS405";
compatible = "qcom,qcs405";
qcom,msm-id = <352 0x0>;
interrupt-parent = <&intc>;
interrupt-parent = <&wakegic>;
chosen {
bootargs = "sched_enable_hmp=1";
@ -125,11 +125,31 @@
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
interrupt-parent = <&intc>;
#interrupt-cells = <3>;
reg = <0x0b000000 0x1000>,
<0x0b002000 0x1000>;
};
wakegic: wake-gic {
compatible = "qcom,mpm-gic-msm8937", "qcom,mpm-gic";
interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
reg = <0x601d0 0x1000>,
<0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */
reg-names = "vmpm", "ipc";
qcom,num-mpm-irqs = <64>;
interrupt-controller;
interrupt-parent = <&intc>;
#interrupt-cells = <3>;
};
wakegpio: wake-gpio {
compatible = "qcom,mpm-gpio-msm8937", "qcom,mpm-gpio";
interrupt-controller;
interrupt-parent = <&intc>;
#interrupt-cells = <2>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 2 0xff08>,