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clk: mxs: Use a better name for the USB PHY clock
Use a better name for the USB PHY clock. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -52,7 +52,7 @@ clocks and IDs.
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lcdif 38
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lcdif 38
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etm 39
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etm 39
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usb 40
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usb 40
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usb_pwr 41
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usb_phy 41
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Examples:
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Examples:
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@ -73,8 +73,8 @@ clocks and IDs.
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can1 59
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can1 59
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usb0 60
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usb0 60
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usb1 61
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usb1 61
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usb0_pwr 62
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usb0_phy 62
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usb1_pwr 63
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usb1_phy 63
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enet_out 64
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enet_out 64
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Examples:
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Examples:
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@ -85,7 +85,7 @@ enum imx23_clk {
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cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll,
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cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll,
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emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div,
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emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div,
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clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif,
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clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif,
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lcdif, etm, usb, usb_pwr,
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lcdif, etm, usb, usb_phy,
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clk_max
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clk_max
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};
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};
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@ -143,8 +143,8 @@ int __init mx23_clocks_init(void)
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clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31);
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clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31);
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clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31);
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clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31);
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clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
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clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
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clks[usb] = mxs_clk_gate("usb", "usb_pwr", DIGCTRL, 2);
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clks[usb] = mxs_clk_gate("usb", "usb_phy", DIGCTRL, 2);
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clks[usb_pwr] = clk_register_gate(NULL, "usb_pwr", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock);
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clks[usb_phy] = clk_register_gate(NULL, "usb_phy", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock);
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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if (IS_ERR(clks[i])) {
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if (IS_ERR(clks[i])) {
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@ -140,7 +140,7 @@ enum imx28_clk {
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emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div,
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emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div,
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clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0,
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clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0,
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ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,
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ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,
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fec, can0, can1, usb0, usb1, usb0_pwr, usb1_pwr, enet_out,
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fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out,
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clk_max
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clk_max
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};
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};
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@ -218,10 +218,10 @@ int __init mx28_clocks_init(void)
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clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30);
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clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30);
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clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30);
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clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30);
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clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28);
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clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28);
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clks[usb0] = mxs_clk_gate("usb0", "usb0_pwr", DIGCTRL, 2);
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clks[usb0] = mxs_clk_gate("usb0", "usb0_phy", DIGCTRL, 2);
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clks[usb1] = mxs_clk_gate("usb1", "usb1_pwr", DIGCTRL, 16);
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clks[usb1] = mxs_clk_gate("usb1", "usb1_phy", DIGCTRL, 16);
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clks[usb0_pwr] = clk_register_gate(NULL, "usb0_pwr", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock);
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clks[usb0_phy] = clk_register_gate(NULL, "usb0_phy", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock);
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clks[usb1_pwr] = clk_register_gate(NULL, "usb1_pwr", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock);
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clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock);
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clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock);
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clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock);
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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