Peter De Schrijver 04edb099a4 clk: tegra: move some PLLC and PLLXC init to clk-pll.c ...

VCO min clipping, dynamic ramp setup and IDDQ init can be done in the
respective PLL clk_register functions if the parent is already registered.
This is done for other some PLLs already.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>

2013-11-26 18:46:21 +02:00

..

clk-audio-sync.c

…

clk-divider.c

…

clk-periph-gate.c

clk: tegra: simplify periph clock data

2013-11-26 18:45:40 +02:00

clk-periph.c

clk: tegra: Add TEGRA_PERIPH_NO_DIV flag

2013-11-26 18:46:20 +02:00

clk-pll-out.c

…

clk-pll.c

clk: tegra: move some PLLC and PLLXC init to clk-pll.c

2013-11-26 18:46:21 +02:00

clk-super.c

clk: tegra: Implement locking for super clock

2013-02-12 10:29:12 -07:00

clk-tegra20.c

clk: tegra: common periph_clk_enb_refcnt and clks

2013-11-26 18:46:18 +02:00

clk-tegra30.c

clk: tegra: common periph_clk_enb_refcnt and clks

2013-11-26 18:46:18 +02:00

clk-tegra114.c

clk: tegra: move some PLLC and PLLXC init to clk-pll.c

2013-11-26 18:46:21 +02:00

clk.c

clk: tegra: common periph_clk_enb_refcnt and clks

2013-11-26 18:46:18 +02:00

clk.h

clk: tegra: Add TEGRA_PERIPH_NO_DIV flag

2013-11-26 18:46:20 +02:00

Makefile

clk: tegra: Implement clocks for Tegra114

2013-04-04 17:17:12 -06:00