Chris Wilson 63256ec534 drm/i915: Enforce write ordering through the GTT ...

We need to ensure that writes through the GTT land before any
modification to the MMIO registers and so must impose a mandatory write
barrier when flushing the GTT domain. This was revealed by relaxing the
write ordering by experimentally mapping the registers and the GATT as
write-combining.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

2011-01-11 20:42:53 +00:00

..

drm

drm/i915: Enforce write ordering through the GTT

2011-01-11 20:42:53 +00:00

stub

drm/stub/Kconfig: fix Kconfig for stub driver.

2010-11-09 13:33:00 +10:00

vga

vga_switcheroo: comparing too few characters in strncmp()

2011-01-07 15:29:37 +10:00

Makefile

gpu: Add Intel GMA500(Poulsbo) Stub Driver

2010-10-26 11:00:13 +10:00