Peter De Schrijver 7ba28813b4 clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE ...

Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are
always functional.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

2013-04-04 16:10:42 -06:00

..

clk-audio-sync.c

clk: tegra: add Tegra specific clocks

2013-01-28 11:19:07 -07:00

clk-divider.c

clk: tegra: add Tegra specific clocks

2013-01-28 11:19:07 -07:00

clk-periph-gate.c

clk: tegra: Fix periph_clk_to_bit macro

2013-04-04 16:08:27 -06:00

clk-periph.c

clk: tegra: Export peripheral reset functions

2013-04-04 16:08:31 -06:00

clk-pll-out.c

clk: tegra: add Tegra specific clocks

2013-01-28 11:19:07 -07:00

clk-pll.c

clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE

2013-04-04 16:10:42 -06:00

clk-super.c

clk: tegra: Implement locking for super clock

2013-02-12 10:29:12 -07:00

clk-tegra20.c

clk: tegra: Refactor PLL programming code

2013-04-04 16:10:33 -06:00

clk-tegra30.c

clk: tegra: Refactor PLL programming code

2013-04-04 16:10:33 -06:00

clk.c

clk: tegra: provide dummy cpu car ops

2013-04-04 16:10:12 -06:00

clk.h

clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE

2013-04-04 16:10:42 -06:00

Makefile

clk: tegra: add clock support for Tegra30

2013-01-28 11:19:07 -07:00