Ard Biesheuvel a3a80544ac arm64: fix typo in I-cache policy detection
This removes an unfortunately placed semi-colon resulting in all instruction
caches being classified as AIVIVT.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2014-08-18 19:47:03 +01:00
..
2014-08-04 12:31:53 -07:00
2014-08-04 12:31:53 -07:00