Peter De Schrijver b29f9e9264 clk: tegra: add TEGRA_PERIPH_NO_GATE
Tegra124 has a clock which consists of a mux and a fractional divider.
Add support for this.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26 18:46:53 +02:00
..
2013-11-26 18:46:51 +02:00
2013-11-26 18:46:52 +02:00
2013-11-26 18:46:53 +02:00