Andre Przywara b2a1c6c349 clk: sunxi: A31: Fix wrong AHB gate number
[ Upstream commit ee0b27a3a4da0b0ed2318aa092f8856896e9450b ]

According to the manual the gate clock for MMC3 is at bit 11, and NAND1
is controlled by bit 12.

Fix the gate bit definitions in the clock driver.

Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-03-23 14:35:13 +01:00
..
2019-02-12 19:46:03 +01:00
2019-02-12 19:46:09 +01:00
2018-12-21 14:13:14 +01:00
2018-09-15 09:45:27 +02:00
2018-12-21 14:13:13 +01:00
2018-11-13 11:15:11 -08:00
2019-03-13 14:03:20 -07:00
2018-10-03 17:00:46 -07:00