Robert Jarzmik
108f303f0e
arm: pxa: add clock pll selection bits
...
Add missing bits for CCCR and CCSR :
- CPLL and PPLL selection, either full speed or 13MHz
- CPSR masks
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-30 12:31:31 -07:00
..
2014-08-08 15:57:26 -07:00
2014-08-09 09:58:12 -07:00
2014-09-30 12:31:31 -07:00
2014-08-13 18:27:40 -06:00
2014-08-09 09:58:12 -07:00
2014-08-09 09:58:12 -07:00
2014-08-09 09:58:12 -07:00
2014-08-09 09:58:12 -07:00
2014-08-09 09:58:12 -07:00
2014-08-09 09:58:12 -07:00
2014-08-14 11:12:46 -06:00
2014-08-09 09:58:12 -07:00
2014-08-09 09:58:12 -07:00
2014-08-13 18:18:09 -06:00
2014-08-09 09:58:12 -07:00
2014-08-09 09:58:12 -07:00
2014-08-09 09:58:12 -07:00
2014-08-09 09:58:12 -07:00
2014-08-09 09:58:12 -07:00
2014-08-14 10:14:07 -06:00
2014-08-09 09:58:12 -07:00
2014-08-09 09:58:12 -07:00
2014-08-11 07:14:01 -07:00
2014-08-13 22:00:09 -07:00
2014-08-09 09:58:12 -07:00
2014-08-09 09:58:12 -07:00
2014-08-09 09:58:12 -07:00
2014-08-16 09:25:34 -06:00
2014-08-09 09:58:12 -07:00
2014-07-18 12:13:37 -07:00