Seungwon Jeon e419990b5e mmc: dw_mmc: correct the calculation for CLKDIV
In case of "host->bus_hz < slot->clock", divider value is
miscalculated. And clock divider register value is multiple of 2. If
calculated divider value is odd number, result can be over-clocking.

Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Acked-by: Will Newton <will.newton@gmail.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
2012-06-06 09:38:51 -04:00
..
2012-02-03 13:33:05 +01:00
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