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Merge "ARM: dts: msm: Add secondary USB configuration for sm8150"

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qctecmdr Service 2018-05-29 13:49:35 -07:00 committed by Gerrit - the friendly Code Review server
commit 50214dcb8f
6 changed files with 296 additions and 0 deletions
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11
arch/arm64/boot/dts/qcom/sm8150-auto.dtsi
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@ -133,6 +133,17 @@
core-supply = <&pm8150_2_l8>;
};
&usb2_phy1 {
vdd-supply = <&pm8150_1_l5>;
vdda18-supply = <&pm8150_1_l12>;
vdda33-supply = <&pm8150_1_l2>;
};
&usb_qmp_phy {
vdd-supply = <&pm8150_1_l5>;
core-supply = <&pm8150_2_l8>;
};
&icnss {
vdd-cx-mx-supply = <&pm8150_1_l1>;
vdd-1.8-xo-supply = <&pm8150_1_l7>;

16
arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi
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@ -38,6 +38,18 @@
qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */
qca,bt-vdd-ldo-current-level = <0>; /* LPM/PFM */
};
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
vbus-gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>;
id-gpio = <&tlmm 101 GPIO_ACTIVE_HIGH>;
vbus-out-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb2_vbus_det_default
&usb2_id_det_default
&usb2_vbus_boost_default>;
};
};
&qupv3_se13_4uart {
@ -552,3 +564,7 @@
};
};
};
&usb1 {
extcon = <&extcon_usb1>;
};

16
arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi
View File

@ -44,6 +44,18 @@
qcom,batt-id-range-pct = <15>;
#include "fg-gen4-batterydata-alium-3600mah.dtsi"
};
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
vbus-gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>;
id-gpio = <&tlmm 101 GPIO_ACTIVE_HIGH>;
vbus-out-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb2_vbus_det_default
&usb2_id_det_default
&usb2_vbus_boost_default>;
};
};
&qupv3_se13_4uart {
@ -571,3 +583,7 @@
&smb1390_charger {
status = "ok";
};
&usb1 {
extcon = <&extcon_usb1>;
};

9
arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi
View File

@ -3938,5 +3938,14 @@
bias-disable;
};
};
usb2_id_det_default: usb2_id_det_default {
config {
pins = "gpio101";
function = "gpio";
input-enable;
bias-pull-up;
};
};
};
};

19
arch/arm64/boot/dts/qcom/sm8150-pmic-overlay.dtsi
View File

@ -37,6 +37,25 @@
power-source = <1>;
};
};
usb2_vbus_boost {
usb2_vbus_boost_default: usb2_vbus_boost_default {
pins = "gpio9";
function = "normal";
output-low;
power-source = <1>; /* 1.8V input supply */
};
};
usb2_vbus_det {
usb2_vbus_det_default: usb2_vbus_det_default {
pins = "gpio10";
function = "normal";
input-enable;
bias-pull-down;
power-source = <1>; /* 1.8V input supply */
};
};
};
&pm8150l_gpios {

225
arch/arm64/boot/dts/qcom/sm8150-usb.dtsi
View File

@ -321,4 +321,229 @@
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
/* Secondary USB port related controller */
usb1: ssusb@a800000 {
compatible = "qcom,dwc-usb3-msm";
reg = <0x0a800000 0x100000>;
reg-names = "core_base";
iommus = <&apps_smmu 0x160 0x0>;
qcom,smmu-s1-bypass;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupts = <0 491 0>, <0 135 0>, <0 487 0>, <0 490 0>;
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
"ss_phy_irq", "dm_hs_phy_irq";
qcom,use-pdc-interrupts;
USB3_GDSC-supply = <&usb30_sec_gdsc>;
clocks = <&clock_gcc GCC_USB30_SEC_MASTER_CLK>,
<&clock_gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&clock_gcc GCC_USB30_SEC_SLEEP_CLK>,
<&clock_gcc GCC_USB3_SEC_CLKREF_CLK>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"utmi_clk", "sleep_clk", "xo";
resets = <&clock_gcc GCC_USB30_SEC_BCR>;
reset-names = "core_reset";
qcom,core-clk-rate = <200000000>;
qcom,core-clk-rate-hs = <66666667>;
qcom,num-gsi-evt-buffs = <0x3>;
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
qcom,charging-disabled;
qcom,msm-bus,name = "usb1";
qcom,msm-bus,num-cases = <3>;
qcom,msm-bus,num-paths = <3>;
qcom,msm-bus,vectors-KBps =
/* suspend vote */
<MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_EBI_CH0 0 0>,
<MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_IPA_CFG 0 0>,
<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3_1 0 0>,
/* nominal vote */
<MSM_BUS_MASTER_USB3_1
MSM_BUS_SLAVE_EBI_CH0 1000000 2500000>,
<MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3_1 0 40000>,
/* svs vote */
<MSM_BUS_MASTER_USB3_1
MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
<MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3_1 0 40000>;
status = "disabled";
dwc3@a800000 {
compatible = "snps,dwc3";
reg = <0x0a800000 0xcd00>;
interrupts = <0 138 0>;
usb-phy = <&usb2_phy1>, <&usb_qmp_phy>;
linux,sysdev_is_parent;
snps,disable-clk-gating;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
usb-core-id = <0>;
maximum-speed = "super-speed";
dr_mode = "otg";
};
};
/* Primary USB port related High Speed PHY */
usb2_phy1: hsphy@88e3000 {
compatible = "qcom,usb-hsphy-snps-femto";
reg = <0x88e3000 0x110>;
reg-names = "hsusb_phy_base";
vdd-supply = <&pm8150_l5>;
vdda18-supply = <&pm8150_l12>;
vdda33-supply = <&pm8150_l2>;
qcom,vdd-voltage-level = <0 880000 880000>;
clocks = <&clock_rpmh RPMH_CXO_CLK>;
clock-names = "ref_clk_src";
resets = <&clock_gcc GCC_QUSB2PHY_SEC_BCR>;
reset-names = "phy_reset";
status = "disabled";
};
/* Secondary USB port related QMP PHY */
usb_qmp_phy: ssphy@88eb000 {
compatible = "qcom,usb-ssphy-qmp-v2";
reg = <0x88eb000 0x1000>,
<0x088eb88c 0x4>;
reg-names = "qmp_phy_base",
"pcs_clamp_enable_reg";
vdd-supply = <&pm8150_l5>;
qcom,vdd-voltage-level = <0 880000 880000>;
core-supply = <&pm8150l_l3>;
qcom,vbus-valid-override;
qcom,qmp-phy-init-seq =
/* <reg_offset, value, delay> */
<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0
USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0
USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06 0
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0
USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0
USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0
USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0
USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0
USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0
USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0x8a 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x3f 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x3f 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0xbf 0
USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0x3f 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb3 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0
USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc 0
USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04 0
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05 0
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0
USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x08 0
USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0
USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04 0
USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0
USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e 0
USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0
USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0
USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x30 0
USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x04 0
USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0
USB3_UNI_QSERDES_TX_LANE_MODE_1 0x05 0
USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0xe4 0
USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0xd0 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x17 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
USB3_UNI_PCS_RX_SIGDET_LVL 0xaa 0
USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0
USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0
USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0
USB3_UNI_PCS_EQ_CONFIG1 0x0d 0
USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0
USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x08 0
0xffffffff 0xffffffff 0x00>;
qcom,qmp-phy-reg-offset =
<USB3_UNI_PCS_PCS_STATUS1
USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
USB3_UNI_PCS_POWER_DOWN_CONTROL
USB3_UNI_PCS_SW_RESET
USB3_UNI_PCS_START_CONTROL>;
clocks = <&clock_gcc GCC_USB3_SEC_PHY_AUX_CLK>,
<&clock_gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
<&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_USB3_SEC_CLKREF_CLK>,
<&clock_gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
"ref_clk", "com_aux_clk";
resets = <&clock_gcc GCC_USB3_PHY_SEC_BCR>,
<&clock_gcc GCC_USB3PHY_PHY_SEC_BCR>;
reset-names = "phy_reset", "phy_phy_reset";
status = "disabled";
};
};