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pinctrl: msm: Restore some barriers to prevent reordering of I/O writes

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Although data dependencies and one-way, semi-permeable barriers provided by
spin locks satisfy most ordering needs here, it is still possible for some
I/O writes to be reordered with respect to one another in a dangerous way.
One such example is that the interrupt status bit could be cleared *after*
the interrupt is unmasked when enabling the IRQ, potentially leading to a
spurious interrupt if there's an interrupt pending from when the IRQ was
disabled.

To prevent dangerous I/O write reordering, restore the minimum amount of
barriers needed to ensure writes are ordered as intended.

Change-Id: I4c44eaa93f39591d5c963dba2b9dcaf33831bdbe
Signed-off-by: Sultan Alsawaf <sultan@kerneltoast.com>
Signed-off-by: Richard Raya <rdxzv.dev@gmail.com>
This commit is contained in:
Sultan Alsawaf 2022-06-16 20:39:32 -07:00 committed by Richard Raya
parent d774137330
commit 874879f16f
1 changed files with 5 additions and 5 deletions
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10
drivers/pinctrl/qcom/pinctrl-msm.c
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@ -518,7 +518,7 @@ static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, in
val = readl_relaxed(base + g->ctl_reg);
val |= BIT(g->oe_bit);
writel_relaxed(val, base + g->ctl_reg);
writel(val, base + g->ctl_reg);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
@ -674,11 +674,11 @@ static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
base = reassign_pctrl_reg(pctrl->soc, d->hwirq);
do {
val = readl_relaxed(base + g->io_reg) & BIT(g->in_bit);
val = readl(base + g->io_reg) & BIT(g->in_bit);
pol = readl_relaxed(base + g->intr_cfg_reg);
pol ^= BIT(g->intr_polarity_bit);
writel_relaxed(pol, base + g->intr_cfg_reg);
writel(pol, base + g->intr_cfg_reg);
val2 = readl_relaxed(base + g->io_reg) & BIT(g->in_bit);
intstat = readl_relaxed(base + g->intr_status_reg);
@ -771,7 +771,7 @@ static void msm_gpio_irq_unmask(struct irq_data *d)
val = readl_relaxed(base + g->intr_cfg_reg);
val |= BIT(g->intr_enable_bit);
writel_relaxed(val, base + g->intr_cfg_reg);
writel(val, base + g->intr_cfg_reg);
set_bit(d->hwirq, pctrl->enabled_irqs);
@ -889,7 +889,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
} else {
BUG();
}
writel_relaxed(val, base + g->intr_cfg_reg);
writel(val, base + g->intr_cfg_reg);
if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
msm_gpio_update_dual_edge_pos(pctrl, g, d);