721106 Commits

Author SHA1 Message Date
Bao D. Nguyen
65b96d600c ARM: dts: msm: Add UFS support for sm8150-auto
Enable UFS device as the primary storage device for sm8150-auto.

Change-Id: Icf12828d84ca966c0db79664968db743ca3ad32a
Signed-off-by: Bao D. Nguyen <nguyenb@codeaurora.org>
Signed-off-by: Hans Chang <hansc@codeaurora.org>
2018-05-31 15:39:09 -07:00
qctecmdr Service
8588eafd1f Merge "arm64: Apply Erratum 1024718 to Kryo4xx Cores" 2018-05-31 14:54:01 -07:00
qctecmdr Service
e7fd076684 Merge "msm: fastcvpd: adding hyp_assign to allow memory access to CDSP" 2018-05-31 14:54:00 -07:00
qctecmdr Service
d30a37bdf2 Merge "power: smb5: Enable Type-C DRP try.snk support" 2018-05-31 14:54:00 -07:00
Subbaraman Narayanamurthy
7749839c75 power: smb5: Expose QNOVO_ENABLE property
Currently, QNOVO is not enabled and hence QNOVO_ENABLE property
is not exposed. However, there are clients (like FG) which can
attempt reading this property and the absence of it creates a log
spew. Fix it by returning 0 through QNOVO_ENABLE property.

Change-Id: Ib9ff11779a62bf49091524a114d346c7bea7d5ec
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
2018-05-31 14:47:27 -07:00
Shashank Babu Chinta Venkata
d774a6450f ARM: dts: msm: alter disable load to 0 for DSI supplies on sm8150
DSI digital supplies currently have disable load set to 4
uA and 32 uA for 1.2v and 0.9v supplies respectively. This
is preventing the suplies from entering low power mode. Thus,
change disable load to 0.

Change-Id: I9032d290775f0307d4ddbf36b424ba6fcd0ae476
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
2018-05-31 14:05:44 -07:00
Runmin Wang
2cadba513b sched: boost: Add a missing break
Add a missing break statement in the last case of the switch
statement.

Change-Id: I466004c6d32059f19c71a5ed6dec0956e4a4d759
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
2018-05-31 12:54:36 -07:00
Isaac J. Manjarres
b6e4755d8a defconfig: Enable minidump support for SM8150 target
Enable Minidump collection support for SM8150, which is used
to collect dumps from on field devices.

Change-Id: Ibdf8463f011eac7df8492235269704ca5876e045
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2018-05-31 11:13:42 -07:00
qctecmdr Service
2db73c74c7 Merge "iommu/arm-smmu: Replace devm_ioremap_resource by devm_ioremap" 2018-05-31 11:10:55 -07:00
qctecmdr Service
e31113fdde Merge "arm64: Add work around for Arm Cortex-A55 Erratum 1024718" 2018-05-31 11:10:54 -07:00
Deepak Katragadda
f6f113ff7b clk: qcom: clk-alpha-pll: Avoid reconfiguring Trion and Regera PLLs
Return early from the Trion and Regera PLL configure operations
if they've been configured already.

Change-Id: I6865571d5d54d548faa297360d65f49ca13a9f0f
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2018-05-31 10:08:49 -07:00
Satya Durga Srinivasu Prabhala
43980276ec sched/sched_avg: make number of running tasks conservative
Right now if a task ran 15% in the previous window, that task is
considered as part of number of running tasks as well as while
calculating misfit tasks on smaller capacity clusters which
agressively un-isolates higher capacity CPUs and may lead to
more power consumption. To avoid such issues, make number of
running tasks conservative by changing threshold to 85%.

Change-Id: Ic82724b822bb605fbda385ddeb50a591757d2c9d
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2018-05-31 08:04:25 -07:00
Satya Durga Srinivasu Prabhala
746245c894 sched/core_ctl: disable prev assist by default
Prev assist is not needed for all clusters with in the system
and can be enabled from user space for specific cluster as needed.
So, disable prev assist by default and update checks as necessary.

Change-Id: I3e3770a0f2dc6f588693c98e3b8514b4fab29fd6
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2018-05-31 08:02:13 -07:00
Satya Durga Srinivasu Prabhala
96a6526f36 sched/core_ctl : make assisting more stringent
Currently, if the task_threshold is very high as compared
to the assist threshold, we could end up in a situation
where the next cluster assists when there are isolated
cores in the prev cluster.

Fix this by setting the assist need to 0 when there are
isolated cpus.

Change-Id: Ic85ce244397a48d2bb28fd68b2c7c49d06c1afa5
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
2018-05-31 07:59:58 -07:00
qctecmdr Service
3a71af90a0 Merge "msm: kgsl: Use the GMU for bus DCVS" 2018-05-31 05:56:23 -07:00
qctecmdr Service
c0948f7067 Merge "ARM: dts: msm: Add glink client device nodes for QCS405" 2018-05-31 05:56:23 -07:00
qctecmdr Service
e798be76da Merge "Revert "drivers: dma-removed: introduce no-map-fixup"" 2018-05-31 05:56:22 -07:00
qctecmdr Service
40942c527b Merge "ARM: dts: msm: add ion secure cma heap node on qcs405" 2018-05-31 05:56:22 -07:00
qctecmdr Service
30f618169c Merge "ARM: dts: msm: support PM6150L BOB dynamic mode configuration on SM6150" 2018-05-31 05:56:21 -07:00
qctecmdr Service
46e1c1ad14 Merge "msm: ipa4: add SMMU support for EMAC" 2018-05-31 05:56:21 -07:00
Taniya Das
d8a81b881f clk: qcom: Update the PMIC XO clocks for QCS405
The PMIC XO buffer clocks are updated as per the PMIC requirements.

Change-Id: I5c90a30bc674d42ec73494476333c9f9f0d98d33
Signed-off-by: Taniya Das <tdas@codeaurora.org>
2018-05-31 14:50:40 +05:30
Pavankumar Kondeti
be8677d4ff arm64: smp: Get ipi_raise tracepoint working again
'commit 741a8ec5bb22 ("ARM64: smp: Prevent cluster LPM modes when
pending IPIs on cluster CPUs")' broke ipi_raise trace point. Get
it working again by replacing __smp_cross_call() with smp_cross_call(),
which has a call to ipi_raise() tracepoint.

While at it, add missing update to pending_ipi flag for IPI_IRQ_WORK.

Change-Id: I4a847e833bf3b21abc58be88dfdc45da9bcfc676
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
2018-05-31 01:46:40 -07:00
Tharun Kumar Merugu
1ebb4b73ee ARM: dts: msm: ADSPRPC: CDSP loader DT entry for qcs405
Add CDSP loader DT entry to load CDSP image in the boot for qcs405.

Change-Id: Ie6fac88460679e9fb3674bff099ab908307a0c37
Acked-by: Himateja Reddy <hmreddy@qti.qualcomm.com>
Signed-off-by: Tharun Kumar Merugu <mtharu@codeaurora.org>
2018-05-30 22:56:07 -07:00
Sachin Grover
08823210bc selinux: KASAN: slab-out-of-bounds in xattr_getsecurity
Call trace:
 [<ffffff9203a8d7a8>] dump_backtrace+0x0/0x428
 [<ffffff9203a8dbf8>] show_stack+0x28/0x38
 [<ffffff920409bfb8>] dump_stack+0xd4/0x124
 [<ffffff9203d187e8>] print_address_description+0x68/0x258
 [<ffffff9203d18c00>] kasan_report.part.2+0x228/0x2f0
 [<ffffff9203d1927c>] kasan_report+0x5c/0x70
 [<ffffff9203d1776c>] check_memory_region+0x12c/0x1c0
 [<ffffff9203d17cdc>] memcpy+0x34/0x68
 [<ffffff9203d75348>] xattr_getsecurity+0xe0/0x160
 [<ffffff9203d75490>] vfs_getxattr+0xc8/0x120
 [<ffffff9203d75d68>] getxattr+0x100/0x2c8
 [<ffffff9203d76fb4>] SyS_fgetxattr+0x64/0xa0
 [<ffffff9203a83f70>] el0_svc_naked+0x24/0x28

If user get root access and calls security.selinux setxattr() with an
embedded NUL on a file and then if some process performs a getxattr()
on that file with a length greater than the actual length of the string,
it would result in a panic.

To fix this, add the actual length of the string to the security context
instead of the length passed by the userspace process.

Change-Id: Ie0b8bfc7c96bc12282b955fb3adf41b3c2d011cd
Signed-off-by: Sachin Grover <sgrover@codeaurora.org>
2018-05-30 22:09:17 -07:00
qctecmdr Service
1eb51a0caa Merge "clk: qcom: clk-smd-rpm: Support new XO voter clock for CDSP" 2018-05-30 18:27:46 -07:00
qctecmdr Service
3923cf20a5 Merge "fbdev: msm: Remove restore secure cfg stub out" 2018-05-30 18:27:46 -07:00
qctecmdr Service
fe7dcefb7d Merge "coresight: place pm_runtime_put() properly" 2018-05-30 18:27:45 -07:00
qctecmdr Service
a01b88eb38 Merge "esoc: power down on reboot" 2018-05-30 18:27:45 -07:00
qctecmdr Service
797184940b Merge "trace: events: pdc: Correct trace print" 2018-05-30 18:27:45 -07:00
qctecmdr Service
afbb764d9c Merge "defconfig: add DCC_V2 support on qcs405" 2018-05-30 18:27:44 -07:00
Tingwei Zhang
37c53a1c6e defconfig: Enable QDSS bridge driver
Enable QDSS bridge driver on SM8150.  This driver provides
communication interface from MHI QDSS channel to USB.

Change-Id: I092b2d88383a9055169e15d0041652b4c6ce7bb3
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
2018-05-30 18:24:59 -07:00
Tingwei Zhang
1c4a015123 soc: qcom: Migrate to MHI device driver
MHI bus has been introduced. Migrate qdss bridge driver to
new MHI interface. Register it as MHI device driver.

Change-Id: If103b8e342dd6242bdba23d01fe74dc840c972b9
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
2018-05-31 09:23:55 +08:00
Vaibhav Deshu Venkatesh
a6832ce6ec msm: vidc: Update enc work mode and route selection
Work_Route is 1 for VP8 or Slice Mode is Max Bytes.
Work_Mode is 1 for VP8 usecases with resolution UHD and under.
Enable Low Latency when slice mode is Max Bytes.

CRs-Fixed: 2232041 2243429
Change-Id: Ia191ed601d7aed405594bee4659aaac1efb6a4e0
Signed-off-by: Vaibhav Deshu Venkatesh <vdeshuve@codeaurora.org>
Signed-off-by: Chinmay Sawarkar <chinmays@codeaurora.org>
2018-05-30 18:21:19 -07:00
Namratha Siddappa
603598fd37 Merge remote-tracking branch 'quic/dev/msm-4.14-display' into msm-4.14
* quic/dev/msm-4.14-display:
  drm/msm/sde: update plane scaler configs when disabled
  msm: sde: delimit the va_arg list in smmu fault handler
  drm/msm/dsi-staging: move misr caching to pre clk_off
  ARM: dts: msm: add PA dither DT entry for SM8150

Change-Id: I5d204f546677c7e185510222a66e8cf188d7d118
Signed-off-by: Namratha Siddappa <namratha@codeaurora.org>
2018-05-30 17:23:29 -07:00
Harry Yang
810169d119 power: smb5: Enable Type-C DRP try.snk support
Support type-c module in DRP (Dual Role Power) with try.snk enabled.

Try.SNK allows a DRP that has a policy based preference to be a Sink
when connecting to another DRP to effect a transition from a
destined Source role to the Sink role.

CRs-Fixed: 2251295
Change-Id: I4db2e94985e066ba8c4e06490515e6f428026002
Signed-off-by: Harry Yang <harryy@codeaurora.org>
2018-05-30 17:17:33 -07:00
Linux Build Service Account
e00d2a357f Merge "drm/msm/dsi-staging: move misr caching to pre clk_off" into dev/msm-4.14-display 2018-05-30 17:10:32 -07:00
Linux Build Service Account
ad07d26e8c Merge "ARM: dts: msm: add PA dither DT entry for SM8150" into dev/msm-4.14-display 2018-05-30 17:10:29 -07:00
Linux Build Service Account
3f61364a4e Merge "drm/msm/sde: update plane scaler configs when disabled" into dev/msm-4.14-display 2018-05-30 17:10:22 -07:00
Linux Build Service Account
d61bd440e8 Merge "msm: sde: delimit the va_arg list in smmu fault handler" into dev/msm-4.14-display 2018-05-30 17:10:18 -07:00
Guru Das Srinagesh
e148e353cf power: smb5: Enable updating of RECHARGE_SOC PSY property
Currently, reading the POWER_SUPPLY_PROP_RECHARGE_SOC property returns
a static, cached value initially set to the threshold value specified in
the device tree. Update this cached value whenever the threshold value
is successfully written to.

Also, move the setting of the threshold value to a separate function.

CRs-Fixed: 2249337
Change-Id: I2a476f59cde21540ee10d0623724105df7933b14
Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org>
2018-05-30 17:09:40 -07:00
Deepak Katragadda
beb3e1828e clk: qcom: npucc-sm8150: Minor change to the CRC enable sequence
As part of the CRC enable sequence for the npu_cc_cal_dp_clk_src
RCG, the clock driver currently sets the RCGs rate to the VDD_MIN
frequency. However, that's not a corner that's supported on all
versions of the target. Set the RCG to the lowest supported
frequency instead.

Change-Id: I2c318a2b5870fc7ab2ea1481235725fc4eb9a7d0
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2018-05-30 16:50:40 -07:00
Maheshwar Ajja
dc0c2baa2c msm: vidc: Correct conditional check
The buffer type is not bit mask value and hence
do not use bitwise operations for buffer type check.
bitwise check condition sometimes resulting in queuing
input buffer in msm_comm_qbuf_decode_batch() function
which is expected to queue output buffers only.

Change-Id: I73548f725a9f58e5466c9afae226e5f386f126ed
Signed-off-by: Maheshwar Ajja <majja@codeaurora.org>
2018-05-30 15:39:35 -07:00
Namratha Siddappa
18f4458d45 Merge remote-tracking branch 'quic/msm-4.14' into dev/msm-4.14-display
* quic/msm-4.14:
  ARM: dts: msm: Enable sec usb port in host mode on sm8150-auto-adp-star
  defconfig: enable additional features to automotive
  ARM: dts: msm: Add MPM interrupt controller for qcs405
  defconfig: Enable MPM support for qcs405
  msm: vidc: Allocate dsp hfi queues from cdsp memory
  ARM: dts: msm: Add cdsp memory node to video subsystem
  msm: vidc: Add qcom,msm-vidc,mem-cdsp node
  sched/core_ctl: Pass sorted clusters based on capacity to cluster_init
  arch: arm: add support for sdxprairie target
  ARM: dts: msm: Add secondary USB configuration for sm8150
  ion: add support for secure dma allocations
  Revert "mm/memblock: fix a race between search and remove"
  Revert "mm/memblock: disable local irqs while late memblock changes"

Change-Id: I39908fb3d4dfb8fa7d9694dab079c214c8d67ac9
Signed-off-by: Namratha Siddappa <namratha@codeaurora.org>
2018-05-30 15:08:48 -07:00
Isaac J. Manjarres
423ddb934b ARM: dts: msm: Enable dload_type selection on SM8150
Add dload_type device tree node to allow support for
selecting whether a full ramdump, minidump, or both
should be collected from a target.

Change-Id: I314ded251928364f0f8b106964ebd45294a389fc
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2018-05-30 15:05:23 -07:00
Isaac J. Manjarres
326f0dc416 qcom: minidump: Fix stack pointer arithmetic to avoid underflow
Currently, the stack pointer value that is being passed in
might be 0, or might be some value that is not a kernel
address, but it would still be useful to attempt to dump
the process' stack. Add check to use current stack pointer
if given value is not a kernel address. Also, the PAGE_ALIGN
macro up-aligns a value that is passed into it, which is not
correct, so use correct arithmetic to obtain aligned stack
pointer value, and add sanity check to ensure that the stack
pointer is within the process stack to avoid underflow errors
that may lead to registering a large amount of minidump
entries.

Change-Id: I211464cbff669a5dd4ffa0919ffea4f79fe55db1
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2018-05-30 15:05:10 -07:00
qctecmdr Service
f0ba2637fb Merge "cpuidle: lpm-levels: Use of_node_put on node pointers" 2018-05-30 15:03:19 -07:00
qctecmdr Service
cb9a5e94b8 Merge "defconfig: arm64: Enable TGU in sm8150 perf config" 2018-05-30 15:03:19 -07:00
qctecmdr Service
70a7fbc34a Merge "power: fg-util: Update fg_get_battery_type" 2018-05-30 15:03:19 -07:00
Isaac J. Manjarres
cf016771ea arm64: Apply Erratum 1024718 to Kryo4xx Cores
Add kryo4xx MIDR value to the list of CPUs that
are impacted by erratum 1024718.

Change-Id: Id9972b199c21733c710326a9934d9981cfcf8b48
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2018-05-30 14:35:50 -07:00
Isaac J. Manjarres
da02701a21 arm64: Add MIDR values for kryo4xx little cores
Add MIDR value for kryo4xx little cores to apply errata
workarounds that may affect little cores.

Change-Id: Ib92539172c42699122aa94658a061685b3efe0fe
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
2018-05-30 14:35:50 -07:00